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ADS1255IDB 参数 Datasheet PDF下载

ADS1255IDB图片预览
型号: ADS1255IDB
PDF下载: 下载PDF文件 查看货源
内容描述: 极低噪声, 24位模拟数字转换器 [Very Low Noise, 24-Bit Analog-to-Digital Converter]
分类和应用: 转换器
文件页数/大小: 39 页 / 422 K
品牌: BB [ BURR-BROWN CORPORATION ]
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ꢐꢕ ꢙꢚ ꢋ ꢛ ꢛ  
ꢐꢕ ꢙꢚ ꢋ ꢛ ꢜ  
www.ti.com  
SBAS288D − JUNE 2003 − REVISED AUGUST 2004  
5.76MHz, 7.68MHz, are the same. The digital filter will  
attenuate high-frequency noise on the ADS1255/6 inputs  
up to the frequency where the response repeats. If  
significant noise on the inputs is present above this  
frequency, make sure to remove with external filtering.  
Fortunately, this can be done on the ADS1255/6 with a  
simple RC filter, as shown in the Applications Section (see  
Figure 25).  
Table 13. Settling Time vs Data Rate  
DATA RATE  
(SPS)  
SETTLING TIME (t  
)
18  
(ms)  
30,000  
15,000  
7500  
3750  
2000  
1000  
500  
100  
60  
0.21  
0.25  
0.31  
0.44  
0.68  
1.18  
0
2.18  
20  
40  
60  
80  
10.18  
16.84  
20.18  
33.51  
40.18  
66.84  
100.18  
200.18  
400.18  
50  
30  
25  
15  
100  
120  
140  
10  
5
2.5  
0
1.92  
3.84  
5.76  
7.68  
NOTE: f  
CLKIN  
= 7.68MHz.  
Frequency (MHz)  
Settling Time Using Synchronization  
Figure 16. Frequency Response Out to 7.68MHz  
for Data Rate = 30kSPS  
The SYNC/PDWN pin allows direct control of conversion  
timing. Simply issue a Sync command or strobe the  
SYNC/PDWN pin after changing the analog inputs (see  
the Synchronization section for more information). The  
conversion begins when SYNC/PDWN is taken high,  
stopping the current conversion and restarting the digital  
filter. As soon as SYNC/PDWN goes low, the DRDY  
output goes high and remains high during the conversion.  
After the settling time (t18), DRDY goes low, indicating that  
data is available. The ADS1255/6 settles in a single  
cycle—there is no need to ignore or discard data after  
synchronization. Figure 18 shows the data retrieval  
sequence following synchronization.  
0
20  
40  
60  
80  
100  
120  
140  
0
1.92  
3.84  
5.76  
7.68  
AINP −AINN  
SYNC/PDWN  
t18  
Frequency (MHz)  
Figure 17. Frequency Response Out to 7.68MHz  
for Data Rate = 2.5SPS  
DRDY  
SETTLING TIME  
The ADS1255/6 features a digital filter optimized for fast  
settling. The settling time (time required for a step change  
on the analog inputs to propagate through the filter) for the  
different data rates is shown in Table 13. The following  
sections highlight the single-cycle settling ability of the  
filter and show various ways to control the conversion  
process.  
RDATA  
DIN  
Settled  
Data  
DOUT  
Figure 18. Data Retrieval After Synchronization  
20  
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