ꢐ ꢕꢙ ꢚꢋ ꢛꢛ
ꢐ ꢕꢙ ꢚꢋ ꢛꢜ
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SBAS288D − JUNE 2003 − REVISED AUGUST 2004
Self-Calibration
Table 20. Self Gain Calibration Timing
Self-calibration corrects internal offset and gain errors.
During self-calibration, the appropriate calibration signals
are applied internally to the analog inputs.
PGA SETTING
4
DATA RATE
(SPS)
1
2
8
16, 32, 64
651µs
30,000
15,000
7500
3750
2000
1000
500
100
60
417µs
484µs
617µs
417µs
484µs
617µs
451µs
517µs
551µs
617µs
SELFOCAL performs a self offset calibration. The analog
inputs AINP and AINN are disconnected from the signal
source and connected to AVDD/2. See Table 19 for the
time required for self offset calibration for the different data
rate settings. As with most of the ADS1255/6 timings, the
calibration time scales directly with fCLKIN. Self offset
calibration updates the OFC register.
484µs
551µs
617µs
751µs
884
1.4ms
2.4ms
4.5ms
21.0ms
34.1ms
41.7ms
67.8ms
83.0ms
135.3ms
207.0ms
413.7ms
827.0ms
Table 19. Self Offset and System Offset
Calibration Timing
50
30
DATA RATE
(SPS)
SELF OFFSET CALIBRATION AND
SYSTEM OFFSET CALIBRATION TIME
25
15
30,000
15,000
7500
3750
2000
1000
500
100
60
387µs
453µs
10
5
587µs
2.5
853µs
NOTE: For f
= 7.68MHz.
CLKIN
1.3ms
2.3ms
SELFCAL performs first a self offset and then a self gain
calibration. The analog inputs are disconnected from the
from the signal source during self-calibration. When using
the input buffer with self-calibration, make sure to observe
the common-mode range of the reference inputs as
described above. Table 21 shows the time required for
self-calibration for the different data rate settings.
Self-calibration updates both the OFC and FSC registers.
4.3ms
20.3ms
33.7ms
40.3ms
67.0ms
80.3ms
133.7ms
200.3ms
400.3ms
800.3ms
50
30
25
15
10
Table 21. Self-Calibration Timing
5
2.5
PGA SETTING
4
DATA RATE
(SPS)
1
2
8
16, 32, 64
892µs
NOTE: For f
CLKIN
= 7.68MHz.
30,000
15,000
7500
3750
2000
1000
500
100
60
596µs
696µs
896µs
596µs
696µs
896µs
692µs
696µs
762µs
896µs
696µs
896µs
SELFGCAL performs a self gain calibration. The analog
inputs AINP and AINN are disconnected from the signal
source and AINP is connected internally to VREFP while
AINN is connected to VREFN. Self gain calibration can be
used with any PGA setting, and the ADS1255/6 has
excellent gain calibration even for the higher PGA settings,
as shown in the Typical Characteristics section. Using the
buffer will limit the common-mode range of the reference
inputs during self gain calibration since they will be
connected to the buffer inputs and must be within the
specified analog input range. When the voltage on VREFP
or VREFN exceeds the buffer analog input range
(AVDD – 2.0V), the buffer must be turned off during self
gain calibration. Otherwise, use system gain calibration or
write the gain coefficients directly to the FSC register.
Table 20 shows the time required for self gain calibration
for the different data rate and PGA settings. Self gain
calibration updates the FSC register.
896µs
1029µs
1.3ms
2.0ms
3.6ms
6.6ms
31.2ms
50.9ms
61.8ms
101.3ms
123.2ms
202.1ms
307.2ms
613.8ms
1227.2ms
50
30
25
15
10
5
2.5
NOTE: For f
= 7.68MHz.
CLKIN
25
BB [ BURR-BROWN CORPORATION ]
