ꢐ ꢕꢙ ꢚꢋ ꢛꢛ
ꢐ ꢕꢙ ꢚꢋ ꢛꢜ
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SBAS288D − JUNE 2003 − REVISED AUGUST 2004
DATA READY (DRDY)
STANDBY MODE
The DRDY output is used as a status signal to indicate
when conversion data is ready to be read. DRDY goes low
when new conversion data is available. It is reset high
when all 24 bits have been read back using Read Data
(RDATA) or Read Data Continuous (RDATAC) command.
It also goes high when the new conversion data is being
updated. Do not retrieve during this update period as the
data is invalid. If data is not retrieved, DRDY will only be
high during the update time as shown in Figure 24.
The standby mode shuts down all of the analog circuitry
and most of the digital features. The oscillator continues to
run to allow for fast wakeup. If enabled, clock output
D0/CLKOUT will also continue to run during during
Standby mode. To enter Standby mode, issue the
STANDBY command. To exit Standby mode, issue the
WAKEUP command. DRDY will stay high after exiting
Standby mode until valid data is ready. Standby mode can
be used to perform one-shot conversions; see Settling
Time Using One-Shot Mode section for more details.
Data Updating
POWER-DOWN MODE
Holding the SYNC/PDWN pin low for 20 DRDY cycles
activates the Power-Down mode. During Power-Down
mode, all circuitry is disabled including the oscillator and
the clock output.
DRDY
Figure 24. DRDY with No Data Retreival
To exit Power-Down mode, take the SYNC/PDWN pin
high. Upon exiting from Power-Down mode, the
ADS1255/6 crystal oscillator typically requires 30ms to
wake up. If using an external clock source, 8192 CLKIN
cycles are needed before conversions begin.
After changing the PGA, data rate, buffer status, writing to
the OFC or FSC registers, and enabling or disabling the
sensor detect circuitry, perform
a synchronization
operation to force DRDY high. It will stay high until valid
data is ready. If auto-calibration is enabled (by setting the
ACAL bit in the ADCON register), DRDY will go low after
the self-calibration is complete and new data is valid.
Exiting from Reset, Synchronization, Standby or
Power-Down mode will also force DRDY high. DRDY will
go low as soon as valid data is ready.
RESET
There are three methods to reset the ADS1255/6: the
RESET input pin, RESET command, and a special SCLK
reset pattern.
When using the RESET pin, take it low to force a reset.
Make sure to follow the minimum pulse width timing
specifications before taking the RESET pin back high.
SYNCHRONIZATION
The RESET command takes effect after all eight bits have
been shifted into DIN. Afterwards, the reset releases
automatically.
Synchronization of the ADS1255/6 is available to
coordinate the A/D conversion with an external event and
also to speed settling after an instantaneous change on
the analog inputs (see Conversion Time using
Synchronization section).
The ADS1255/6 can also be reset with a special pattern on
SCLK (see Figure 2). Reset occurs on the falling edge of
the last SCLK edge in the pattern. After performing the
operation, the reset releases automatically.
Synchronization can be achieved either using the
SYNC/PDWN pin or with the SYNC command. To use the
SYNC/PDWN pin, take it low and then high, making sure
to meet timing specification t16. Synchronization occurs on
the first rising edge of the master clock after SYNC/PDWN
is taken high. No communication is possible on the serial
interface while SYNC/PDWN is low. If the SYNC/PDWN
pin is held low for 20 DRDY periods the ADS1255/6 will
enter Power-Down mode.
On reset, the configuration registers are initialized to their
default state except for the CLK0 and CLK1 bits in the
ADCON register that control the D0/CLKOUT pin. These
bits are only initialized to the default state when RESET is
performed using the RESET pin. After releasing from
RESET, self-calibration is performed, regardless of the
reset method or the state of the ACAL bit before RESET.
To synchronize using the SYNC command, first shift in all
eight bits of the SYNC command. This stops the operation
of the ADS1255/6. When ready to synchronize, issue the
WAKEUP command. Synchronization occurs on the first
rising edge of the master clock after the first SCLK used to
shift in the WAKEUP command. After a synchronization
operation, either with the SYNC/PDWN pin or the SYNC
command, DRDY stays high until valid data is ready.
POWER-UP
All of the configuration registers are initialized to their
default state at power-up. A self-calibration is then
performed automatically. For the best performance, it is
strongly recommended to perform an additional
self-calibration by issuing the SELFCAL command after
the power supplies and voltage reference have had time
to settle to their final values.
27
BB [ BURR-BROWN CORPORATION ]
