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SBAS288D − JUNE 2003 − REVISED AUGUST 2004
repeats with a period of τSAMPLE. This time is a function of
the PGA setting as shown in Table 9 along with the values
of the capacitor CA1 = CA2 = CA and CB.
PROGRAMMABLE GAIN AMPLIFIER (PGA)
The ADS1255/6 is a very high resolution converter. To
further complement its performance, the low-noise PGA
provides even more resolution when measuring smaller
input signals. For the best resolution, set the PGA to the
highest possible setting. This will depend on the largest
input signal to be measured. The ADS1255/6 full-scale
input voltage equals 2VREF/PGA. Table 8 shows the
full-scale input voltage for the different PGA settings for
VREF = 2.5V. For example, if the largest signal to be
measured is 1.0V, the optimum PGA setting would be 4,
which gives a full-scale input voltage of 1.25V. Higher
PGAs cannot be used since they cannot handle a 1.0V
input signal.
AVDD/2
AIN0
AIN1
AIN2
AIN3
S2
C
A1
AIN
P
S1
S1
Input
C
AIN4
AIN5
B
Multiplexer
AIN
N
AIN6
C
S2
AIN7
A2
Table 8. Full-Scale Input Voltage vs
PGA Setting
AINCOM
AVDD/2
PGA SETTING FULL-SCALE INPUT VOLTAGE (V
REF
= 2.5V)
1
2
5V
2.5V
Figure 9. Simplified Input Structure
with Buffer Off
4
1.25V
8
0.625V
312.5mV
156.25mV
78.125mV
16
32
64
τ SAMPLE
ON
S1
S2
OFF
ON
The PGA is controlled by the ADCON register.
Recalibrating the A/D converter after changing the PGA
setting is recommended. The time required for
self-calibration is dependent on the PGA setting. See the
Calibration section for more details. The analog current
and input impedance (when the buffer is disabled) vary as
a function of PGA setting.
OFF
Figure 10. S1 and S2 Switch Timing for Figure 9
Table 9. Input Sampling Time, τ
, and
SAMPLE
C and C vs PGA
A
B
MODULATOR INPUT CIRCUITRY
PGA
The ADS1255/6 modulator measures the input signal
using internal capacitors that are continuously charged
and discharged. Figure 9 shows a simplified schematic of
the ADS1255/6 input circuitry with the input buffer
disabled. Figure 10 shows the on/off timings of the
switches of Figure 9. S1 switches close during the input
sampling phase. With S1 closed, CA1 charges to AINP,CA2
charges to AINN, and CB charges to (AINP – AINN). For the
discharge phase, S1 opens first and then S2 closes. CA1
and CA2 discharge to approximately AVDD/2 and CB
discharges to 0V. This two-phase sample/discharge cycle
(1)
SETTING
τ
C
C
B
SAMPLE
A
1
2
f
f
f
f
f
f
f
/4 (521ns)
/4 (521ns)
/4 (521ns)
/4 (521ns)
/4 (521ns)
/2 (260ns)
/2 (260ns)
2.1pF
4.2pF
8.3pF
17pF
33pF
33pF
33pF
2.4pF
4.9pF
9.7pF
19pF
39pF
39pF
39pF
CLKIN
CLKIN
CLKIN
CLKIN
CLKIN
CLKIN
CLKIN
4
8
16
32
64
(1)
τ
for f = 7.68MHz.
CLKIN
SAMPLE
16
BB [ BURR-BROWN CORPORATION ]
