SERIAL INTERFACE
ISOLATION
The serial interface of the ADS1254 provides for simple
isolation methods. The CLK signal can be local to the
ADS1254, which then only requires two signals (SCLK and
DOUT/DRDY) to be used for isolated data acquisition. The
channel select signals (CHSEL0, CHSEL1) will also need to
be isolated unless a counter is used to auto multiplex the
channels.
The ADS1254 includes a simple serial interface that can be
connected to microcontrollers and digital signal processors
in a variety of ways. Communications with the ADS1254
can commence on the first detection of the DOUT/DRDY
pulse after power up.
It is important to note that the data from the ADS1254 is a
24-bit result transmitted MSB-first in Offset Two’s Comple-
ment format, as shown in Table IV.
DIFFERENTIAL VOLTAGE INPUT
DIGITAL OUTPUT (HEX)
The data must be clocked out before the ADS1254 enters
DRDY mode to ensure reception of valid data, as described
in the DOUT/DRDY section of this data sheet.
+Full Scale
Zero
–Full Scale
7FFFFFH
000000H
800000H
TABLE IV. ADS1254 Data Format (Offset Two's Comple-
ment).
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tOSC
tDRDY
DRDY Mode
DOUT Mode
CLK Period
Conversion Cycle
DRDY Mode
DOUT Mode
DOR Write Time
DOUT/DRDY LOW Time
125
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
384 • tOSC
36 • tOSC
348 • tOSC
6 • tOSC
6 • tOSC
6 • tOSC
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
DOUT/DRDY HIGH Time (Prior to Data Out)
DOUT/DRDY HIGH Time (Prior to Data Ready)
Rising Edge of CLK to Falling Edge of DOUT/DRDY
End of DRDY Mode to Rising Edge of First SCLK
End of DRDY Mode to Data Valid (Propagation Delay)
Falling Edge of SCLK to Data Valid (Hold Time)
Falling Edge of SCLK to Next Data Out Valid (Propagation Delay)
SCLK Setup Time for Synchronization or Power Down
DOUT/DRDY Pulse for Synchronization or Power Down
Rising Edge of SCLK Until Start of Synchronization
Synchronization Time
Falling Edge of CLK (After SCLK Goes Low) Until Start of DRDY Mode
Rising Edge of SCLK Until Start of Power Down
Falling Edge of CLK (After SCLK Goes Low) Until Start of DRDY Mode
Falling Edge of Last DOUT/DRDY to Start of Power Down
DOUT/DRDY High Time After Mux Change.
24 • tOSC
50
50
50
30
5
30
3 • tOSC
1537 • CLK
0.5 • CLK
7679 • CLK
6143.5 • CLK
2042.5 • tOSC
7681 • CLK
2318.5 • tOSC
6144.5 • tOSC
2043.5 • tosc
TABLE III. Digital Timing.
t18
DATA
DATA
DOUT/DRDY
CHSEL0, CHSEL1
MUX CHANGE
FIGURE 13. Multiplexer Operation.
ADS1254
12
SBAS213
BB [ BURR-BROWN CORPORATION ]
