DIGITAL FILTER RESPONSE
DIGITAL FILTER RESPONSE
0
–20
0
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–180
–200
–100
–120
–140
–160
–180
–200
55
56
57
58
59
60
61
62
63
64
65
55
56
57
58
59
60
61
62
63
64
65
Frequency (Hz)
Frequency (Hz)
FIGURE 10. Expanded Digital Filter Response (60Hz with
a 60Hz Data Output Rate).
FIGURE 11. Expanded Digital Filter Response (60Hz with
a 10Hz Data Output Rate).
frequency should be 19.200kHz, this will set the data-output
rate to 50Hz (see Table I and Figure 5). For 60Hz rejection,
the system CLK frequency should be 23.040kHz, this will set
the data-output rate to 60Hz (see Table I and Figure 6). If both
50Hz and 60Hz rejection is required, then the system CLK
should be 3.840kHz; this will set the data-output rate to 10Hz
and reject both 50Hz and 60Hz (See Table I and Figure 7).
The digital filter is described by the following transfer func-
tion:
5
π • f •64
sin
fMOD
H f =
( )
π • f
64•sin
or
fMOD
There is an additional benefit in using a lower data-output
rate. It provides better rejection of signals in the frequency
band of interest. For example, with a 50Hz data-output rate,
a significant signal at 75Hz may alias back into the passband
at 25Hz. This is due to the fact that rejection at 75Hz may only
be 66dB in the stopband—frequencies higher than the first-
notch frequency (see Figure 5). However, setting the data-
output rate to 10Hz will provide 135dB rejection at 75Hz (see
Figure 7). A similar benefit is gained at frequencies near the
data-output rate (see Figures 8, 9, 10, and 11). For example,
with a 50Hz data-output rate, rejection at 55Hz may only be
105dB (see Figure 8). However, with a 10Hz data-output rate,
rejection at 55Hz will be 122dB (see Figure 9). If a slower
data-output rate does not meet the system requirements, then
the analog front end can be designed to provide the needed
attenuation to prevent aliasing. Additionally, the data-output
rate may be increased and additional digital filtering may be
done in the processor or controller.
5
1– z–64
H z =
( )
64• 1– z–1
(
)
The digital filter requires five conversions to fully settle. The
modulator has an oversampling ratio of 64, therefore, it
requires 5 • 64, or 320 modulator results, or clocks, to fully
settle. Since the modulator clock is derived from the system
clock (CLK) (modulator clock = CLK ÷ 6), the number of
system clocks required for the digital filter to fully settle is
5 • 64 • 6, or 1920 CLKs. This means that any significant
step change at the analog input requires five full conversions
to settle. However, if the step change at the analog input
occurs asynchronously to the DOUT/DRDY pulse, six con-
versions are required to ensure full settling.
ADS1254
10
SBAS213
BB [ BURR-BROWN CORPORATION ]
