DELTA-SIGMA MODULATOR
REFERENCE INPUT
The ADS1254 operates from a nominal system clock fre-
quency of 8MHz. The modulator frequency is fixed in
relation to the system clock frequency. The system clock
frequency is divided by 6 to derive the modulator frequency.
Therefore, with a system clock frequency of 8MHz, the
modulator frequency is 1.333MHz. Furthermore, the
oversampling ratio of the modulator is fixed in relation to the
modulator frequency. The oversampling ratio of the modu-
lator is 64, and with the modulator frequency running at
1.333MHz, the data rate is 20.8kHz. Using a slower system
clock frequency will result in a lower data output rate, as
shown in Table II.
Reference input takes an average current of 32µA with a
8MHz system clock. This current will be proportional to the
system clock. A buffered reference is recommended for the
ADS1254. The recommended reference circuit is shown in
Figure 3.
Reference voltages higher than 4.096V will increase the
full-scale range, while the absolute internal circuit noise of
the converter remains the same. This will decrease the noise
in terms of ppm of full scale, which increases the effective
resolution (see the Typical Characteristic “RMS Noise vs
VREF Voltage”).
DIGITAL FILTER
CLK (MHz)
DATA OUTPUT RATE (Hz)
The digital filter of the ADS1254, referred to as a sinc5 filter,
computes the digital result based on the most recent outputs
from the delta-sigma modulator. At the most basic level, the
digital filter can be thought of as simply averaging the
modulator results in a weighted form and presenting this
average as the digital output. The digital output rate, or data
rate, scales directly with the system CLK frequency. This
allows the data output rate to be changed over a very wide
range (five orders of magnitude) by changing the system
CLK frequency. However, it is important to note that the
–3dB point of the filter is 0.2035 times the data output rate,
so the data output rate should allow for sufficient margin to
prevent attenuation of the signal of interest.
8(1)
20,833
19,200
16,000
15,625
12,800
9,600
8,000
6,400
4,800
2,400
1,200
1,000
500
100
60
50
30
25
20
16.67
15
12.50
10
7.372800(1)
6.144000(1)
6.000000(1)
4.915200(1)
3.686400(1)
3.072000(1)
2.457600(1)
1.843200(1)
0.921600
0.460800
0.384000
0.192000
0.038400
0.023040
0.019200
0.011520
0.009600
0.007680
0.006400
0.005760
0.004800
0.003840
Since the conversion result is essentially an average, the
data-output rate determines the location of the resulting
notches in the digital filter (see Figure 4). Note that the first
notch is located at the data-output rate frequency, and
subsequent notches are located at integer multiples of the
data-output rate to allow for rejection of not only the
fundamental frequency, but also harmonic frequencies. In
this manner, the data-output rate can be used to set specific
notch frequencies in the digital filter response.
NOTE: (1) Standard Clock Oscillator.
TABLE II. CLK Rate versus Data Output Rate.
For example, if the rejection of power-line frequencies is
desired, then the data-output rate can simply be set to the
power-line frequency. For 50Hz rejection, the system CLK
+5V
+5V
0.10µF
7
4.99kΩ
2
3
To VREF
Pin 18 of
6
OPA350
10kΩ
the ADS1254
1
+
10µF
0.1µF
+
10µF
0.10µF
4
LM404-4.1
FIGURE 3. Recommended External Voltage Reference Circuit for Best Low-Noise Operation with the ADS1254.
ADS1254
8
SBAS213
BB [ BURR-BROWN CORPORATION ]
