time defined by t4. If more than 24 SCLKs were provided
during DOUT mode, the DOUT/DRDY line would stay
LOW until the time defined by t4.
CONTROL LOGIC
The control logic is used for communications and control of
the ADS1254.
The internal data pointer for shifting data out on
DOUT/DRDY is reset on the falling edge of the time defined
by t1 and t4. This ensures that the first bit of data shifted out
of the ADS1254 after DRDY mode is always the MSB of
new data.
Power-Up Sequence
Prior to power-up, all digital and analog-input pins must be
LOW. During power-up, these signal inputs should never
exceed +AVDD or +DVDD
.
Once the ADS1254 powers up, the DOUT/DRDY line will
pulse LOW on the first conversion for which the data is valid
from the analog input signal.
SYNCHRONIZING MULTIPLE CONVERTERS
The normal state of SCLK is LOW, however, by holding
SCLK HIGH, multiple ADS1254s can be synchronized. This
is accomplished by holding SCLK HIGH for at least four, but
less than twenty, consecutive DOUT/DRDY cycles (see Fig-
ure 14). After the ADS1254 circuitry detects that SCLK has
been held HIGH for four consecutive DOUT/DRDY cycles,
the DOUT/DRDY pin will pulse LOW for 3 CLK cycles and
then be held HIGH, and the modulator will be held in a reset
state. The modulator will be released from reset and synchro-
nization will occur on the falling edge of SCLK. With
multiple converters, the falling edge transition of SCLK must
occur simultaneously on all devices. It is important to note
that prior to synchronization, the DOUT/DRDY pulse of
multiple ADS1254s in the system could have a difference in
timing up to one DRDY period. Therefore, to ensure synchro-
nization, the SCLK should be held HIGH for at least five
DRDY cycles. The first DOUT/DRDY pulse after the falling
edge of SCLK will occur at t14. The first DOUT/DRDY pulse
indicates valid data.
DOUT/DRDY
The DOUT/DRDY output signal alternates between two
modes of operation. The first mode of operation is the Data
Ready mode (DRDY) to indicate that new data has been
loaded into the data-output register and is ready to be read.
The second mode of operation is the Data Output (DOUT)
mode and is used to serially shift data out of the Data Output
Register (DOR). The time domain partitioning of the DRDY
and DOUT function as shown in Figure 12.
See Figure 13 for the basic timing of DOUT/DRDY. During
the time defined by t2, t3, and t4, the DOUT/DRDY pin
functions in DRDY mode. The state of the DOUT/DRDY
pin would be HIGH prior to the internal transfer of new data
to the DOR. The result of the A/D conversion would be
written to the DOR from MSB to LSB in the time defined by
t1 (see Figures 12 and 13). The DOUT/DRDY line would
then pulse LOW for the time defined by t2, and then pulse
HIGH for the time defined by t3 to indicate that new data
was available to be read. At this point, the function of the
DOUT/DRDY pin would change to DOUT mode. Data
would be shifted out on the pin after t7. The device commu-
nicating with the ADS1254 can provide SCLKs to the
ADS1254 after the time defined by t6. The normal mode of
reading data from the ADS1254 would be for the device
reading the ADS1254 to latch the data on the rising edge of
SCLK (since data is shifted out of the ADS1254 on the
falling edge of SCLK). In order to retrieve valid data, the
entire DOR must be read before the DOUT/DRDY pin
reverts back to DRDY mode.
POWER-DOWN MODE
The normal state of SCLK is LOW, however, by holding
SCLK HIGH, the ADS1254 will enter power-down mode.
This is accomplished by holding SCLK HIGH for at least
twenty consecutive DOUT/DRDY periods (see Figure 15).
After the ADS1254 circuitry detects that SCLK has been
held HIGH for four consecutive DOUT/DRDY cycles, the
DOUT/DRDY pin will pulse LOW for 3 CLK cycles and
then be held HIGH, and the modulator will be held in a
reset state. If SCLK is held HIGH for an additional sixteen
DOUT/DRDY periods, the ADS1254 will enter
power-down mode. The part will be released from power-
down mode on the falling edge of SCLK. It is important to
note that the DOUT/DRDY pin will be held HIGH after four
DOUT/DRDY cycles, but power-down mode will not be
entered for an additional sixteen DOUT/DRDY periods. The
first DOUT/DRDY pulse after the falling edge of SCLK will
occur at t16 and will indicate valid data. Subsequent DOUT/
DRDY pulses will occur normally.
If SCLKs were not provided to the ADS1254 during the
DOUT mode, the MSB of the DOR would be present on the
DOUT/DRDY line until the time defined by t4. If an incom-
plete read of the ADS1254 took place while in DOUT mode
(i.e., less than 24 SCLKs were provided), the state of the last
bit read would be present on the DOUT/DRDY line until the
DRDY Mode
t4
DRDY Mode
DOUT Mode
DOUT Mode
t2
t3
DATA
DATA
DATA
DOUT/DRDY
t1
FIGURE 12. DOUT/DRDY Partitioning.
ADS1254
11
SBAS213
BB [ BURR-BROWN CORPORATION ]
