ADS1230
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SBAS366–OCTOBER 2006
OFFSET CALIBRATION
During this time, the analog input pins are
disconnected within the ADC and the appropriate
signal is applied internally to perform the calibration.
When the calibration is completed, DRDY/DOUT
goes low, indicating that new data are ready. The
first conversion after a calibration is fully settled and
valid for use. The offset calibration takes exactly the
same time as specified in (tCAL) immediately after the
falling edge of the 26th SCLK.
Offset calibration can be initiated at any time to
remove the ADS1230 inherited offset error. To
initiate offset calibration, apply at least two additional
SCLKs after retrieving 20 bits of data plus four bits of
'1'. Figure 27 shows the timing pattern. The 25th
SCLK keeps DRDY/DOUT high. The falling edge of
the 26th SCLK begins the calibration cycle.
Additional SCLK pulses may be sent after the 26th
SCLK; however, activity on SCLK should be
minimized during offset calibration for best results.
Data Ready After Calibration
DRDY/DOUT
SCLK
19
18
17
0
19
1
2
3
4
Calibration Begins
1
20
21
22
23
24
25
26
tCAL
Figure 27. Offset-Calibration Timing
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
ms
SPEED = 1
SPEED = 0
101.28
801.02
101.29
801.03
(1)
tCAL
First data ready after calibration
ms
(1) Value given for fCLK = 4.9152MHz. For different fCLK frequencies, scale proportional to CLK period. Expect a ±3% variation when an
internal oscillator is used.
16
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