ADS1230
www.ti.com
SBAS366–OCTOBER 2006
SETTLING TIME
DATA FORMAT
In certain instances, large changes in input will
require settling time. For example, an external
multiplexer in front of the ADS1230 can put large
changes in input voltage by simply switching the
multiplexer input channels. Abrupt changes in the
input will require four data conversion cycles to
settle. When continuously converting, five readings
may be necessary in order to settle the data. If the
change in input occurs in the middle of the first
conversion, four more full conversions of the
fully-settled input are required to get fully-settled
data. Discard the first four readings because they
contain only partially-settled data. Figure 23
illustrates the settling time for the ADS1230 in
Continuous Conversion mode.
The ADS1230 outputs 20 bits of data in binary two’s
complement format. The least significant bit (LSB)
has a weight of 0.5VREF/(219 – 1). The positive
full-scale input produces an output code of 7FFFFh
and the negative full-scale input produces an output
code of 800000h. The output clips at these codes for
signals exceeding full-scale. Table 4 summarizes the
ideal output codes for different input signals.
The ADS1230 is a 20-bit ADC. After data conversion
is completed, applying 20 SCLKs retrieves 20 bits of
data (MSB first). However, if the SCLKs continue to
be applied after 20 bits of data are retrieved, the
DOUT pin outputs four 1s for the 21st through the
24th SCLK, as shown in Figure 24.
Table 4. Ideal Output Code vs Input Signal(1)
DATA RATE
INPUT SIGNAL VIN
(AINP – AINN)
≥ +0.5VREF/Gain
(+0.5VREF/Gain)/(219– 1)
0
IDEAL OUTPUT
7FFFFh
The ADS1230 data rate is set by the SPEED pin, as
shown in Table 3. When SPEED is low, the data rate
is nominally 10SPS. This data rate provides the
lowest noise, and also has excellent rejection of both
50Hz and 60Hz line-cycle interference. For
applications requiring fast data rates, setting SPEED
high selects a data rate of nominally 80SPS.
00001h
00000h
(–0.5VREF/Gain)/(219– 1)
≤– 0.5VREF/Gain
FFFFFh
80000h
(1) Excludes effects of noise, INL, offset,
and gain errors.
Table 3. Data Rate Settings
DATA RATE
SPEED
PIN
Internal Oscillator
or 4.9152MHz Crystal
External
Oscillator
0
1
10SPS
80SPS
fCLKIN / 491,520
fCLKIN / 61,440
Abrupt Change in External VIN
VIN
2nd Conversion;
VIN settled, but
digital filter
3rd Conversion;
VIN settled, but
digital filter
4th Conversion;
VIN settled, but
digital filter
5th Conversion;
VIN and digital
filter both
1st Conversion;
includes
Start of
Conversion
unsettled VIN
.
unsettled.
unsettled.
unsettled.
settled.
DRDY/DOUT
Conversion
Time
Figure 23. Settling Time in Continuous Conversion Mode
Data
Data Ready
New Data Ready
MSB
19
LSB
0
DRDY/DOUT
18
17
1
2
3
4
1
2
3
20
21
22
23
24
SCLK
Figure 24. Data Retrieval Format
13
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