ADS1230
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SBAS366–OCTOBER 2006
POWER-DOWN MODE
from locking up to an unknown state. Power-Down
mode can be initiated at any time during readback; it
is not necessary to retrieve all 20 bits of data
beforehand. Figure 30 shows the wake-up timing
from Power-Down mode.
Power-Down mode shuts down the entire ADC
circuitry and reduces the total power consumption
close to zero. To enter Power-Down mode, simply
hold the PDWN pin low. Power-Down mode also
resets the entire circuitry to free the ADC circuitry
Start
Conversion
Data Ready
CLK Source
Power-Down Mode
tPDWN
Wakeup
PDWN
DRDY/DOUT
SCLK
tTS_RDY
tWAKEUP
Figure 30. Wake-Up Timing from Power-Down Mode
SYMBOL
DESCRIPTION
MIN
TYP
7.95
0.16
UNITS
µs
Internal clock
External clock
Wake-up time after Power-Down
mode
tWAKEUP
µs
(1)
tPDWN
PDWN pulse width
26
µs
(1) Value given for fCLK = 4.9152MHz. For different fCLK frequencies, scale proportional to CLK period. Expect a ±3% variation when an
internal oscillator is used.
19
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