ADS1230
www.ti.com
SBAS366–OCTOBER 2006
FREQUENCY RESPONSE
0
Data Rate = 10SPS
The ADS1230 uses a sinc4 digital filter with the
frequency response (fCLK = 4.9152MHz) shown in
Figure 21. The frequency response repeats at
multiples of the modulator sampling frequency of
76.8kHz. The overall response is that of a low-pass
filter with a –3dB cutoff frequency of 3.32Hz with the
SPEED pin tied low (10SPS data rate) and 11.64Hz
with the SPEED pin tied high (80SPS data rate).
-50
-100
-150
0
fCLK = 4.9152MHz
-20
-40
0
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90 100
Frequency (Hz)
-60
(a)
-80
-100
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-50
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-150
Data Rate = 10SPS
0
38.4
76.8
Frequency (kHz)
Figure 21. Frequency Response
To help see the response at lower frequencies,
Figure 22(a) illustrates the response out to 100Hz,
when the data rate = 10SPS. Notice that signals at
multiples of 10Hz are rejected, and therefore
simultaneous rejection of 50Hz and 60Hz is
achieved.
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Frequency (Hz)
(b)
Figure 22. Frequency Response Out To 100Hz
The benefit of using a sinc4 filter is that every
frequency notch has four zeros on the same location.
This response, combined with the low drift internal
oscillator, provides an excellent normal-mode
rejection of line-cycle interference.
The ADS1230 data rate and frequency response
scale directly with clock frequency. For example, if
fCLK increases from 4.9152MHz to 6.144MHz when
the SPEED pin is tied high, the data rate increases
from 80SPS to 100SPS, while notches also increase
from 80Hz to 100Hz. Note that these changes are
only possible when the external clock source is
applied.
Figure 22(b) shows the same plot, but zooms in on
the 50Hz and 60Hz notches with the SPEED pin tied
low (10SPS data rate). With only a ±3% variation of
the internal oscillator, over 100dB of normal-mode
rejection is achieved.
12
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