ADS1230
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SBAS366–OCTOBER 2006
DATA READY/DATA OUTPUT (DRDY/DOUT)
DATA RETRIEVAL
This digital output pin serves two purposes. First, it
indicates when new data are ready by going low.
Afterwards, on the first rising edge of SCLK, the
DRDY/DOUT pin changes function and begins
outputting the conversion data, most significant bit
(MSB) first. Data are shifted out on each subsequent
SCLK rising edge. After all 20 bits have been
retrieved, the pin can be forced high with an
additional SCLK. It then stays high until new data are
ready. This configuration is useful when polling on
the status of DRDY/DOUT to determine when to
begin data retrieval.
The ADS1230 continuously converts the analog input
signal. To retrieve data, wait until DRDY/DOUT goes
low, as shown in Figure 25. After DRDY/DOUT goes
low, begin shifting out the data by applying SCLKs.
Data are shifted out MSB first. It is not required to
shift out all 20 bits of data, but the data must be
retrieved before new data are updated (within tCONV
)
or else the data will be overwritten. Avoid data
retrieval during the update period (tUPDATE). If 24
SCLKs have been applied, DRDY/DOUT will be high
since the last four bits have been appended by '1'.
However, if only 20 SCLKs have been applied,
DRDY/DOUT remains at the state of the last bit
shifted out until it is taken high (see tUPDATE),
indicating that new data are being updated. To avoid
having DRDY/DOUT remain in the state of the last
bit, the 21st SCLK can be applied to force
DRDY/DOUT high, as shown in Figure 26. This
technique is useful when a host controlling the
device is polling DRDY/DOUT to determine when
data are ready.
SERIAL CLOCK INPUT (SCLK)
This digital input shifts serial data out with each
rising edge. As with CLK, this input may be driven
with 5V logic regardless of the DVDD or AVDD
voltage. This input has built-in hysteresis, but care
should still be taken to ensure a clean signal.
Glitches or slow-rising signals can cause unwanted
additional shifting. For this reason, it is best to make
sure the rise and fall times of SCLK are both less
than 50ns.
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