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SBAS282D − JUNE 2003 − REVISED MARCH 2004
Bits 6-5: INP
CONFIGURATION REGISTER
INP controls which two of the four analog inputs are used
to measure data in the ADC. This is shown in Table 7. By
selecting these bits, the ADS1112 can be used to measure
two differential channels or three single ended channels
referenced to AIN3.
The 8-bit configuration register can be used to control the
ADS1112 operating mode, input selection, data rate, and
PGA settings. The configuration register format is shown
in Table 6. The default setting is 8CH.
BIT
7
ST/DRDY
1
6
INP1
0
5
INP0
0
4
SC
0
3
2
1
PGA1
0
0
PGA0
0
INP1
INP0
V
V
IN−
IN+
NAME
DR1 DR0
(1)
(1)
0
0
AIN0
AIN2
AIN0
AIN1
AIN1
AIN3
AIN3
AIN3
DEFAULT
1
1
0
1
1
1
0
1
Table 6. Configuration Register
(1)
Default setting.
Bit 7: ST/DRDY
Table 7. INP Bits.
The meaning of the ST/DRDY bit depends on whether it is
being written to or read from.
Bit 4: SC
In single conversion mode, writing a 1 to the ST/DRDY bit
causes a conversion to start, and writing a 0 has no effect.
In continuous conversion mode, the ADS1112 ignores the
value written to ST/DRDY.
SC controls whether the ADS1112 is in continuous
conversion or single conversion mode. When SC is 1, the
ADS1112 is in single conversion mode; when SC is 0, it is
in continuous conversion mode. The default setting is 0.
When read, ST/DRDY indicates whether the data in the
output register is new data. If ST/DRDY is 0, the data just
read from the output register is new, and has not been read
before. If ST/DRDY is 1, the data just read from the output
register has been read before.
Bits 3-2: DR
Bits 3 and 2 control the ADS1112 data rate, as shown in
Table 8.
DR1
DR0
DATA RATE
240SPS
60SPS
RESOLUTION
12 Bits
The ADS1112 sets ST/DRDY to 0 when it writes data into
the output register. It sets ST/DRDY to 1 after any of the
bits in the configuration register have been read. (Note that
the read value of the bit is independent of the value written
to this bit.)
0
0
1
0
1
0
14 Bits
30SPS
15 Bits
(1)
(1)
(1)
(1)
1
1
15SPS
16 Bits
(1)
Default setting.
In continuous-conversion mode, use ST/DRDY to
determine when new conversion data is ready. If
ST/DRDY is 1, the data in the output register has already
been read, and is not new. If it is 0, the data in the output
register is new, and has not yet been read.
Table 8. INP Bits.
Bits 1-0: PGA
Bits 1 and 0 control the ADS1112 gain setting, as shown
in Table 9.
In single-conversion mode, use ST/DRDY to determine
when a conversion has completed. If ST/DRDY is 1, the
output register data is old, and the conversion is still in
process; if it is 0, the output register data is the result of the
new conversion.
PGA1
PGA0
GAIN
(1)
(1)
(1)
0
0
1
0
1
1
1
0
1
2
4
8
Note that the output register is returned from the ADS1112
before the configuration register. The state of the
ST/DRDY bit applies to the data just read from the output
register, and not to the data from the next read operation.
(1)
Default setting.
Table 9. PGA Bits
11
BB [ BURR-BROWN CORPORATION ]
