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SBAS282D − JUNE 2003 − REVISED MARCH 2004
An I2C bus consists of two lines, SDA and SCL. SDA
carries data; SCL provides the clock. All data is
transmitted across the I2C bus in groups of eight bits. To
send a bit on the I2C bus, the SDA line is driven to the
appropriate level while SCL is LOW (a LOW on SDA
indicates the bit is zero; a HIGH indicates the bit is one).
Once the SDA line has settled, the SCL line is brought
HIGH, then LOW. This pulse on SCL clocks the SDA bit
into the receiver’s shift register.
USING THE ADS1112
OPERATING MODES
The ADS1112 operates in one of two modes: continuous-
conversion or single-conversion.
In continuous-conversion mode, the ADS1112 continu-
ously performs conversions. Once a conversion has been
completed, the ADS1112 places the result in the output
register and immediately begins another conversion.
The I2C bus is bidirectional: the SDA line is used both for
transmitting and receiving data. When a master reads from
a slave, the slave drives the data line; when a master
sends to a slave, the master drives the data line. The
master always drives the clock line. The ADS1112 never
drives SCL, because it cannot act as a master. On the
ADS1112, SCL is an input only.
In single-conversion mode, the ADS1112 waits until the
ST/DRDY bit in the conversion register is set to 1. When
this happens, the ADS1112 powers up and performs a
single conversion. After the conversion completes, the
ADS1112 places the result in the output register, resets the
ST/DRDY bit to 0, and powers down. Writing a 1 to
ST/DRDY while a conversion is in progress has no effect.
Most of the time the bus is idle; no communication occurs
place, and both lines are HIGH. When communication is
taking place, the bus is active. Only master devices can
start a communication and initiate a START condition on
the bus. Normally, the data line is only allowed to change
state while the clock line is LOW. If the data line changes
state while the clock line is HIGH, it is either a START
condition or its counterpart, a STOP condition. A START
condition occurs when the clock line is HIGH and the data
line goes from HIGH to LOW. A STOP condition occurs
when the clock line is HIGH and the data line goes from
LOW to HIGH.
When switched from continuous-conversion mode to
single conversion mode, the ADS1112 completes the
current conversion, resets the ST/DRDY bit to 0, and
powers down.
RESET AND POWER-UP
When the ADS1112 powers up, it automatically performs
a reset. As part of the reset process, the ADS1112 sets all
of the bits in the configuration register to their default
settings.
The ADS1112 responds to the I2C General Call Reset
command. When the ADS1112 receives a General Call
Reset, it performs an internal reset, exactly as though it
had just been powered on.
After the master issues a START condition, it sends a byte
that indicates which slave device it wants to communicate
with. This byte is called the address byte. Each device on
an I2C bus has a unique 7-bit address to which it responds.
(Slaves can also have 10-bit addresses; see the I2C
specification for details.) The master sends an address in
the address byte, together with a bit that indicates whether
it wishes to read from or write to the slave device.
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I C INTERFACE
The ADS1112 communicates through an I2C
(inter-integrated circuit) interface. I2C is a two-wire
open-drain interface supporting multiple devices and
masters on a single bus. Devices on the I2C bus only drive
the bus lines LOW by connecting them to ground; they
never drive the bus lines HIGH. Instead, the bus wires are
pulled HIGH by pull-up resistors, so the bus wires are
HIGH when no device is driving them LOW. This way, two
devices cannot conflict; if two devices drive the bus
simultaneously, there is no driver contention.
Every byte transmitted on the I2C bus, whether it is
address or data, is acknowledged with an acknowledge
bit. When a master has finished sending a byte (eight data
bits) to a slave, it stops driving SDA and waits for the slave
to acknowledge the byte. The slave acknowledges the
byte by pulling SDA LOW. The master then sends a clock
pulse to clock the acknowledge bit. Similarly, when a
master has finished reading a byte, it pulls SDA LOW to
acknowledge this to the slave. It then sends a clock pulse
to clock the bit. (The master always drives the clock line.)
Communication on the I2C bus always takes place
between two devices, one acting as the master and the
other as the slave. Both masters and slaves can read and
write, but slaves can only do so under the direction of the
master. Some I2C devices can act as masters or slaves,
but the ADS1112 can only act as a slave device.
A not-acknowledge is performed by simply leaving SDA
HIGH during an acknowledge cycle. If a device is not
present on the bus, and the master attempts to address it,
it will receive a not-acknowledge because no device is
present at that address to pull the line LOW.
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BB [ BURR-BROWN CORPORATION ]
