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SBAS282D − JUNE 2003 − REVISED MARCH 2004
When a master has finished communicating with a slave,
it may issue a STOP condition. When a STOP condition is
issued, the bus becomes idle again. A master may also
issue another START condition. When a START condition
is issued while the bus is active, it is called a repeated
START condition.
addresses to be selected with only two pins as shown in
Table 4. The state of pins A0 and A1 is sampled on
power-up or after an I2C general call, and should be set
prior to any activity on the interface.
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I C GENERAL CALL
A timing diagram for an ADS1112 I2C transaction is shown
in Figure 1. The parameters for this diagram are given in
Table 3.
The ADS1112 responds to the I2C General Call address
(0000000) if the eighth bit is 0. The device will
acknowledge the General Call address and respond to
commands in the second byte. If the second byte is
00000100 (04h), the ADS1112 will latch the status of the
address pins, A0 and A1, but not perform a reset. If the
second byte is 00000110 (06h), the ADS1112 will latch the
status of the address pins and reset the internal registers.
SERIAL BUS ADDRESS
To program the ADS1112, the master must first address
slave devices via a slave address byte. The slave address
byte consists of seven address bits, and a direction bit
indicating the intent of executing a read or write operation.
The ADS1112 features two address pins, A0 and A1, that
set the I2C address. These pins can be set to a logic low,
logic high, or left unconnected (floating), allowing eight
2
Figure 1. I C Timing Diagram
FAST MODE
HIGH-SPEED MODE
MIN
MAX
MIN
MAX
PARAMETER
UNITS
SCLK operating frequency
0.4
3.4
MHz
t
(SCLK)
Bus free time between START and STOP condition
600
600
160
160
ns
ns
t
(BUF)
Hold time after repeated START condition.
After this period, the first clock is generated.
t
(HDSTA)
Repeated START condition setup time
Stop condition setup time
Data hold time
600
600
0
160
160
0
ns
ns
ns
ns
ns
ns
ns
ns
t
(SUSTA)
t
(SUSTO)
t
(HDDAT)
Data setup time
100
1300
600
10
t
(SUDAT)
SCLK clock LOW period
SCLK clock HIGH period
Clock/data fall time
160
60
t
(LOW)
t
(HIGH)
300
300
160
160
t
F
Clock/data rise time
t
R
Table 3. Timing Diagram Definitions
9
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