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AS8NVLC512K32QC-20XT 参数 Datasheet PDF下载

AS8NVLC512K32QC-20XT图片预览
型号: AS8NVLC512K32QC-20XT
PDF下载: 下载PDF文件 查看货源
内容描述: 512K ×32模块的nvSRAM 3.3V高速SRAM与非易失性存储 [512K x 32 Module nvSRAM 3.3V High Speed SRAM with Non-Volatile Storage]
分类和应用: 存储静态存储器
文件页数/大小: 17 页 / 362 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
 浏览型号AS8NVLC512K32QC-20XT的Datasheet PDF文件第5页浏览型号AS8NVLC512K32QC-20XT的Datasheet PDF文件第6页浏览型号AS8NVLC512K32QC-20XT的Datasheet PDF文件第7页浏览型号AS8NVLC512K32QC-20XT的Datasheet PDF文件第8页浏览型号AS8NVLC512K32QC-20XT的Datasheet PDF文件第10页浏览型号AS8NVLC512K32QC-20XT的Datasheet PDF文件第11页浏览型号AS8NVLC512K32QC-20XT的Datasheet PDF文件第12页浏览型号AS8NVLC512K32QC-20XT的Datasheet PDF文件第13页  
SEMICONDUCTOR, INC.  
ADVANCE INFORMATION  
nvSRAM  
AS8nvLC512K32  
Austin Semiconductor, Inc.  
AC Switching Characteristics  
Parameters  
20ns  
25ns  
45ns  
AustinSemiꢀ  
Altꢀ  
Parameters Parameters  
Description  
Min  
Max  
Min  
Max  
Min  
Max  
Unit  
SRAMReadCycle  
tACE  
tACS  
tRC  
tAA  
tOE  
tOH  
tLZ  
tHZ  
tOLZ  
tOHZ  
tPA  
tPS  
Ͳ
ChipEnableAccessTime  
20  
25  
45  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
13  
tRCꢀ  
ReadCycleTime  
20  
25  
45  
14  
tAA  
AddressAccessTime  
20  
10  
25  
12  
45  
20  
tDOE  
OutputEnabletoDataValid  
OutputHoldAfterAddressChange  
ChipEnabletoOutputActive  
ChipDisabletoOutputActive  
OutputEnabletoOutputActive  
OutputDisabletoOutputInactive  
ChipEnabletoPowerActive  
ChipDisabletoPowerStandby  
ByteEnabletoDataValid  
tOHA14  
tLZCE12,15  
tHZCE12,15  
tLZOE12,15  
tHZOE12,15  
tPU12  
2
2
2
2
2
2
8
8
10  
10  
15  
15  
0
0
0
0
0
0
tPD12  
20  
10  
25  
12  
45  
20  
tDBE  
tLZBE12  
tHZBE12  
Ͳ
ByteEnabletoOutputActive  
ByteDisabletoOutputInactive  
0
0
0
Ͳ
8
10  
15  
SRAMWriteCycle  
tWC  
tPWE  
tSCE  
tSD  
tWC  
tWP  
tCW  
tDW  
tDH  
tAW  
tAS  
WriteCycleTime  
20  
15  
15  
8
25  
20  
20  
10  
0
45  
30  
30  
15  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WritePulseWidth  
ChipEnabletoEndofWrite  
DataSetuptoEndofWrite  
DataHoldAfterEndofWrite  
AddressSetuptoEndofWrite  
AddressSetuptoEndofWrite  
AddressHoldAfterEndofWrite  
WriteEnabletoOutputDisable  
OutputActiveafterEndofWrite  
ByteEnabletoEndofWrite  
tHD  
0
tAW  
tSA  
15  
0
20  
0
30  
0
tHA  
tWR  
tWZ  
tOW  
Ͳ
0
0
0
12,15,16  
tHZWEꢀ  
8
10  
15  
12,15  
tLZWEꢀ  
tBW  
2
2
2
15  
20  
30  
Switching Waveforms  
SRAM Read Cycle #1: Address Controlled13, 14, 17  
tRC  
Address  
Address Valid  
tAA  
Output Data Valid  
Previous Data Valid  
tOHA  
Data Output  
Notes  
13.WE\ must be HIGH during SRAM read cycles.  
14. Device is continuously selected with CE\, OE\ LOW.  
15.Measured 200 mV from steady state output voltage.  
16. If WE\ is LOW when CE\ goes LOW, the outputs remain in the high impedance state.  
17. HSB\ must remain HIGH during read and write cycles.  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
AS8nvLC512K32  
Rev. 0.0 08/09  
9