AS4LC1M16 883C
1 MEG x 16 DRAM
AUSTIN SEMICONDUCTOR, INC.
PRELIMINARY
BYTE ACCESS CYCLE
WRITE on one byte and a LATE WRITE on the other byte is
not allowed during the same cycle. However, an EARLY
WRITE on one byte and, after a CAS precharge has been
satisfied, a LATE WRITE on the other byte is permissable.
The BYTE WRITEs and BYTE READs are determined by
the use of CASL and CASH. Enabling CASL will select a
lower BYTE access (DQ1-DQ8). Enabling CASH will select
an upper BYTE access (DQ9-DQ16). Enabling both CASL
and CASH selects a WORD WRITE cycle.
The AS4LC1M16 may be viewed as two 1 Meg x 8
DRAMs that have common input controls, with the excep-
tion ofthe CASinputs. Figure 3illustrates the BYTEWRITE
and WORD WRITE cycles.
Additionally, both bytes must always be of the same
mode ofoperation ifboth bytes are active. A CASprecharge
must be satisfied prior to changing modes of operation
between the upper and lower bytes.For example,an EARLY
REFRESH
Preserve correct memory cell data by maintaining power
and executing a RAS cycle (READ, WRITE) or RAS refresh
cycle (RAS ONLY, CBR, or HIDDEN) so that all 1,024
combinations of RAS addresses are executed at least every
16ms, regardless ofsequence. The CBRREFRESH cycle will
invoke the refresh counter for automatic RAS addressing.
WORD WRITE
LOWER BYTE WRITE
RAS
CASL
CASH
WE
STORED
INPUT
INPUT
DATA
STORED STORED
INPUT
INPUT
DATA
STORED
DATA
DATA
DATA
DATA
DATA
DATA
1
1
0
1
1
1
1
1
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
LOWER BYTE
(DQ1-DQ8)
OF WORD
X
X
X
X
X
X
X
X
1
0
1
0
1
1
1
1
1
0
1
0
1
1
1
1
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
X
1
0
1
0
1
1
1
1
0
1
0
1
0
0
0
0
UPPER BYTE
(DQ9-DQ16)
OF WORD
ADDRESS 0
X = NOT EFFECTIVE (DON'T CARE)
ADDRESS 1
Figure 3
WORD AND BYTE WRITE EXAMPLE
AS4LC1M16
REV. 3/97
DS000020
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-96
AUSTIN [ AUSTIN SEMICONDUCTOR ]
