AS4LC1M16 883C
1 MEG x 16 DRAM
AUSTIN SEMICONDUCTOR, INC.
PRELIMINARY
GENERAL DESCRIPTION (continued)
The CASL and CASH inputs internally generate a CAS
signal functioning in a similar manner to the single
PAGE ACCESS
PAGE operations allow faster data operations (READ,
WRITE or READ-MODIFY-WRITE) within a row-address-
defined page boundary.The PAGEcycle is always initiated
with a row -address strobed-in by RAS followed by a col-
umn-address strobed-in by CAS. CAS may be toggled-in
by holding RAS LOW and strobing-in different column-
addresses, thus executing faster memory cycles. Returning
RAS HIGH terminates the PAGE MODE of operation.
?C?A/S input of other DRAMs. The key difference is each
CAS input ( CASL and CASH ) controls its corresponding
8 DQ inputs during WRITE accesses. CASL controls DQ1
through DQ8 and CASH controls DQ9 through DQ16. The
two CAS controls give the MT4LC1M16E5(S) both BYTE
READ and BYTE WRITE cycle capabilities.
A logic HIGH on WE dictates READ mode while a logic
LOW on WE dictates WRITE mode. During a WRITE cycle,
data-in (D) is latched by the falling edge of WE or CAS
(CASLor CASH),whichever occurs last.An EARLYWRITE
occurs when WE is taken LOW prior to either CAS falling.
A LATE WRITE or READ-MODIFY-WRITE occurs when
WE falls after CAS (CASL or CASH) was taken LOW.
During EARLY WRITE cycles, the data-outputs (Q) will
remain High-Z regardless of the state of OE. During LATE
WRITE or READ-MODIFY-WRITE cycles, OE must be
taken HIGH to disable the data-outputs prior to applying
input data. If a LATE WRITE or READ-MODIFY-WRITE is
attempted while keeping OE LOW, no write will occur, and
the data-outputs will drive read data from the accessed
location.
EDO PAGE MODE
The AS4LC1M16 provides EDO PAGE MODE which is
an accelerated FAST PAGE MODE cycle. The primary
advantage of EDO is the availability of data-out even after
CAS returns HIGH. EDO provides for CAS precharge time
t
( CP) to occur without the output data going invalid. This
elimination of CAS output control provides for pipeline
READs.
FAST-PAGE-MODE DRAMs have traditionally turned
the output buffers off (High-Z) with the rising edge of
CAS. EDO-PAGE-MODE DRAMs operate similar to
FAST-PAGE-MODEDRAMs,except data willremain valid
or become valid after CAS goes HIGH during READs,
provided RAS and OE are held LOW. If OE is pulsed while
RAS and CAS are LOW, data will toggle from valid data to
High-Z and back to the same valid data. If OE is toggled or
pulsed after CASgoes HIGH while RASremains LOW,data
will transition to and remain High-Z (refer to Figure 1).
The 16data inputs and 16data outputs are routed through
16 pins using common I/ O. Pin direction is controlled by
OE and WE.
V
V
IH
IL
RAS
CASL/CASH
V
V
IH
IL
V
V
IH
IL
ADDR
ROW
COLUMN (A)
COLUMN (B)
COLUMN (C)
COLUMN (D)
V
V
IOH
IOL
DQ
OPEN
VALID DATA (A)
VALID DATA (A)
VALID DATA (B)
VALID DATA (C)
VALID DATA (D)
t
t
OD
t
OD
OD
t
OES
t
OEHC
V
V
IH
IL
OE
t
OE
t
OEP
The DQs go back to
Low-Z if OES is met.
The DQs remain High-Z
until the next CAS cycle
if OEHC is met.
The DQs remain High-Z
until the next CAS cycle
if OEP is met.
t
t
t
DON’T CARE
UNDEFINED
Figure 1
OUTPUT ENABLE AND DISABLE
AS4LC1M16
REV. 3/97
DS000020
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-94
AUSTIN [ AUSTIN SEMICONDUCTOR ]
