AS4LC1M16 883C
1 MEG x 16 DRAM
AUSTIN SEMICONDUCTOR, INC.
PRELIMINARY
EDO PAGE MODE (continued)
WE can also perform the function of disabling the output
drivers under certain conditions, as shown in Figure 2.
During an application, if the DQ outputs are wire OR’d,
OE must be used to disable idle banks of DRAMs. Alterna-
tively, pulsing WEto the idle banks during CASHIGH time
will also High-Z the outputs. Independent of OE control,
the outputs will disable after OFF, which is referenced
t
from the rising edge of RAS or CAS, whichever occurs last.
V
IH
RAS
CASL/CASH
ADDR
V
IL
V
V
IH
IL
V
V
IH
IL
ROW
COLUMN (A)
COLUMN (B)
COLUMN (C)
COLUMN (D)
V
V
IOH
IOL
DQ
OPEN
VALID DATA (A)
VALID DATA (B)
INPUT DATA (C)
t
t
WHZ
WHZ
t
V
IH
WE
OE
WPZ
V
IL
V
V
IH
IL
t
The DQs go to High-Z if WE falls, and if WPZ is met,
will remain High-Z until CAS goes LOW with
WE HIGH (i.e., until a READ cycle is initiated).
WE may be used to disable the DQs to prepare
for input data in an EARLY WRITE cycle. The DQs
will remain High-Z until CAS goes LOW with
WE HIGH (i.e., until a READ cycle is initiated).
DON’T CARE
UNDEFINED
Figure 2
WE CONTROL OF DQs
AS4LC1M16
REV. 3/97
DS000020
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-95
AUSTIN [ AUSTIN SEMICONDUCTOR ]
