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AS4DDR232M64PBGR-5/IT 参数 Datasheet PDF下载

AS4DDR232M64PBGR-5/IT图片预览
型号: AS4DDR232M64PBGR-5/IT
PDF下载: 下载PDF文件 查看货源
内容描述: 32Mx64 DDR2 SDRAM集成塑封微电路 [32Mx64 DDR2 SDRAM iNTEGRATED Plastic Encapsulated Microcircuit]
分类和应用: 内存集成电路动态存储器双倍数据速率
文件页数/大小: 28 页 / 363 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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iPEM  
2.1 Gb SDRAM-DDR2  
Austin Semiconductor, Inc.  
AS4DDR232M64PBG  
DESELECT  
The DESELEꢁT function (ꢁS# HIGH) prevents new  
commands from being executed by the DDR2 SDRAM. The  
DDR2 SDRAM is effectively deselected. Operations already  
in progress are not affected.  
A subsequent AꢁTIVE command to a different row in the  
same bank can only be issued after the previous active row  
has been closed (precharged). The minimum time interval  
between successive AꢁTIVE commands to the same bank  
is defined by tRꢁ  
NO OPERATION (NOP)  
A subsequent AꢁTIVE command to another bank can be  
issued while the first bank is being accessed, which results  
in a reduction of total row-access overhead. The minimum  
time interval between successive AꢁTIVE commands to  
different banks is defined by tRRD.  
The NO OPERATION (NOP) command is used to instruct  
the selected DDR2 SDRAM to perform a NOP (ꢁS# is LOW;  
RAS#, ꢁAS#, and WE are HIGH). This prevents unwanted  
commands from being registered during idle or wait states.  
Operations already in progress are not affected.  
LOAD MODE (LM)  
The mode registers are loaded via inputs BA1–BA0, and  
A12–A0. BA1–BA0 determine which mode register will be  
programmed. See “Mode Register (MR)”. The LM command  
can only be issued when all banks are idle, and a  
subsequent execute able command cannot be issued until  
tMRD is met.  
FIGURE 10 - ACTIVE COMMAND  
CK#  
CK  
BANK/ROW ACTIVATION  
ACTIVE COMMAND  
CKE  
CS#  
The AꢁTIVE command is used to open (or activate) a row in  
a particular bank for a subsequent access. The value on the  
BA1–BA0 inputs selects the bank, and the address provided  
on inputs A12–A0 selects the row. This row remains active  
(or open) for accesses until a PREꢁHARGE command is  
issued to that bank. A PREꢁHARGE command must be  
issued before opening a different row in the same bank.  
RAS#  
CAS#  
WE#  
ACTIVE OPERATION  
Before any READ or WRITE commands can be issued to a  
bank within the DDR2 SDRAM, a row in that bank must be  
opened (activated), even when additive latency is used. This  
is accomplished via the AꢁTIVE command, which selects  
both the bank and the row to be activated.  
Row  
ADDRESS  
BANK ADDRESS  
Bank  
After a row is opened with an AꢁTIVE command, a READ or  
WRITE command may be issued to that row, subject to the  
tRꢁD specification. tRꢁD (MIN) should be divided by the  
clock period and rounded up to the next whole number to  
determine the earliest clock edge after the AꢁTIVE command  
on which a READ or WRITE command can be entered. The  
same procedure is used to convert other specification limits  
from time units to clock cycles. For example, a tRꢁD (MIN)  
specification of 20ns with a 266 MHz clock (tꢁK = 3.75ns)  
results in 5.3 clocks, rounded up to 6.  
DON’T CARE  
Austin Semiconductor, Inc.  
Austin, Texas 512.339.1188 www.austinsemiconductor.com  
AS4DDR232M64PBG  
Rev. 1.3 6/09  
16  
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