16 Meg FPM DRAM
AS4C4M4
Austin Semiconductor, Inc.
TEST MODE CYCLE11
-60
-70
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX
UNITS
NOTES
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS\
Access time from CAS\
Access time from column address
RAS\ pulse width
115
135
ns
tRC
160
180
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRWC
tRAC
tCAC
tAA
65
20
70
22
3, 4, 10, 12
3, 4, 5, 12
3, 10 ,12
35
38
65
20
20
65
35
45
90
60
65
45
90
65
10K
10K
75
25
10K
10K
tRAS
tCAS
tRSH
tCSH
tRAL
CAS\ pulse width
RAS\ hold time
22
CAS\ hold time
70
Column address to RAS\ lead time
CAS\ to W\ delay time
40
48
7
7
7
tCWD
tRWD
tAWD
tCPWD
tPC
RAS\ to W\ delay time
100
70
Column address to W\ delay time
CAS\ precharge to W\ delay time
Fast Page cycle time
70
50
Fast Page read-modify-write time
RAS\ pulse width (Fast Page Cycle)
Access time from CAS\ precharge
OE\ access time
100
75
tPRWC
tRASP
tCPA
tOEA
tOED
tOEH
100K
40
100K
45
3
20
22
OE\ to data delay
20
20
22
22
OE\ command hold time
NOTES:
1. An initial pause of 200us is required after power-up followed by an 8 RAS\-only refresh or CAS\-before-RAS\ refresh cycles
before proper device operation is achieved.
2. VIH(MIN) and VIL(MAX) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(MIN) and VIL(MAX) and are assumed to be 5ns for all inputs.
3. Measured with a load equivalent to 2 TTL loads and 100pF.
4. Operation within the tRCD(MAX) limit insures that tRAC(MAX) and be met. tRCD(MAX) is specified as a reference point only.
If tRCD is greater than the specified tRCD(MAX) limit, then access time is controlled exclusively by tCAC
5. Assumes that tRCD > tRCD(MAX).
.
6. tOFF(MIN) and tOEZ(MAX) define the time at which the output achieves the open circuit condition and are not referenced VOH
or VOL.
7. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electrical character-
istics only. If tWCS > tWCS(MIN), the cycle is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If tCWD > tCWD(MIN), tRWD > tRWD(MIN) and tAWD > tAWD(MIN), then the cycle is a read-modify-write cycle
and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the
condition of the data out is indeterminate.
(Continued on page 7)
AS4C4M4
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
Rev. 1.1 06/05
6
AUSTIN [ AUSTIN SEMICONDUCTOR ]
