16 Meg FPM DRAM
AS4C4M4
Austin Semiconductor, Inc.
NOTES (continued):
8. Either tRCH or tRRH must be satisfied for a read cycle.
9. These parameters are referenced to CAS\ falling edge in early write cycles and to W\ falling edge in read-modify-write
cycles.
10. Operation within the tRAD(MAX) limit insures that tRAC(MAX) can be met. tRAD(MAX) is specified as a reference point only.
If tRAD is greater than the specified tRAS(MAX) limit, then access time is controlled by tAA.
11. These specifications are applied in the test mode.
12. In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
13. If tRASS > 100 us, then RAS\ precharge time must use tRPS instead of tRP.
14. For RAS\-only refresh and burst CAS\-before-RAS\ refresh mode, 2048 cycles of burst refresh must be executed within
32ms before and after self refresh, in order to meet refresh specification.
15. For distributed CAS\-before-RAS\ with 15.6us interval CAS\-before-RAS\ refresh should be executed with in 15.6us
immediately before and after self refresh in order to meet refresh specification.
READ CYCLE
AS4C4M4
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
Rev. 1.1 06/05
7
AUSTIN [ AUSTIN SEMICONDUCTOR ]
