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AS29LV016JTRGR-55/IT 参数 Datasheet PDF下载

AS29LV016JTRGR-55/IT图片预览
型号: AS29LV016JTRGR-55/IT
PDF下载: 下载PDF文件 查看货源
内容描述: 16兆位( 2M ×8位/ 1M ×16位) CMOS 3.0伏只引导扇区闪存 [16 Megabit (2M x 8-Bit / 1M x 16-Bit) CMOS 3.0 Volt-Only Boot Sector Flash Memory]
分类和应用: 闪存内存集成电路光电二极管
文件页数/大小: 40 页 / 408 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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COTS PEM  
BOOT SECTOR FLASH  
Austin Semiconductor, Inc.  
AS29LV016J  
CHIP ERASE COMMAND SEQUENCE  
Chip erase is a six bus cycle operation. The chip erase  
command sequence is initiated by writing two unlock  
cycles, followed by a set-up command. Two additional  
unlock write cycles are then followed by the chip erase  
command, which in turn invokes the Embedded Erase  
algorithm. The device does not require the system to  
preprogram prior to erase. The Embedded Erase algorithm  
automatically preprograms and verifies the entire memory  
for an all zero data pattern prior to electrical erase. The  
system is not required to provide any controls or timings  
during these operations. Table 9 on page 21 shows the  
address and data requirements for the chip erase  
command sequence.  
After the command sequence is written, a sector erase  
time-out of 50 µs begins. During the time-out period,  
additional sector addresses and sector erase commands  
may be written. Loading the sector erase buffer may be  
done in any sequence, and the number of sectors may  
be from one sector to all sectors. The time between these  
additional cycles must be less than 50 µs, otherwise the  
last address and command might not be accepted, and  
erasure may begin. It is recommended that processor  
interrupts be disabled during this time to ensure all  
commands are accepted. The interrupts can be re-  
enabled after the last Sector Erase command is written.  
If the time between additional sector erase commands  
can be assumed to be less than 50 µs, the system need  
not monitor DQ3. Any command other than Sector  
Erase or Erase Suspend during the time-out period  
resets the device to reading array data. The system  
must rewrite the command sequence and any additional  
sector addresses and commands.  
Any commands written to the chip during the Embedded  
Erase algorithm are ignored. Note that a hardware reset  
during the chip erase operation immediately terminates  
the operation. The Chip Erase command sequence should  
be reinitiated once the device has returned to reading  
array data, to ensure data integrity.  
The system can monitor DQ3 to determine if the sector  
erase timer has timed out. (See DQ3: Sector Erase Timer  
on page 25.) The time-out begins from the rising edge of  
the final WE# pulse in the command sequence.  
The system can determine the status of the erase  
operation by using DQ7, DQ6, DQ2, or RY/BY#. See  
Write Operation Status on page 22 for information on  
these status bits. When the Embedded Erase algorithm  
is complete, the device returns to reading array data and  
addresses are no longer latched.  
Once the sector erase operation has begun, only the  
Erase Suspend command is valid. All other commands  
are ignored. Note that a hardware reset during the sector  
erase operation immediately terminates the operation.  
The Sector Erase command sequence should be  
reinitiated once the device has returned to reading array  
data, to ensure data integrity.  
Figure 4, on page 20 illustrates the algorithm for the erase  
operation. See Erase / Program Operations on page 32  
for parameters, and Figure 17, on page 33 for timing  
When the Embedded Erase algorithm is complete, the  
device returns to reading array data and addresses are  
no longer latched. The system can determine the status  
of the erase operation by using DQ7, DQ6, DQ2, or RY/  
BY#. (Refer to Write Operation Status on page 22 for  
information on these status bits.)  
diagrams.  
SECTOR ERASE COMMAND SEQUENCE  
Sector erase is a six bus cycle operation. The sector  
erase command sequence is initiated by writing two  
unlock cycles, followed by a set-up command. Two addi-  
tional unlock write cycles are then followed by the address  
of the sector to be erased, and the sector erase command.  
Table 9 on page 21 shows the address and data  
requirements for the sector erase command sequence.  
Figure 4 illustrates the algorithm for the erase operation.  
Refer to Erase / Program Operations on page32 for  
parameters, and to Figure 17, on page 33 for timing  
diagrams.  
The device does not require the system to preprogram  
the memory prior to erase. The Embedded Erase algorithm  
automatically programs and verifies the sector for an all  
zero data pattern prior to electrical erase. The system is  
not required to provide any controls or timings during these  
operations.  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
AS29LV016J  
Rev. 0.0 02/09  
19  
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