COTS PEM
BOOT SECTOR FLASH
Austin Semiconductor, Inc.
AS29LV016J
Table 8: Primary Vendor-Specific Extended Query
Addresses
(Word Mode)
40h
Addresses
(Byte Mode)
80h
Data
Description
Query-unique ASCII string "PRI"
0050h
0052h
0049h
0031h
0033h
41h
42h
43h
44h
82h
84h
86h
88h
Major version number, ASCII
Major version number, ASCII
Address Sensitive Unlock
0=Required, 1=Not Required
45h
8Ah
000Ch
Erase Suspend
46h
8Ch
0002h
0=Not Supported, 1=To Read Only, 2=To Read and Write
Sector Protect
47h
48h
8Eh
90h
0001h
0001h
0=Not Supported, X=Number of Sectors Per Group
Sector Temorary Unprotect
00=Not Supported, 01=Supported
Sector Protect / Unprotect Scheme
01=29F040 mode, 02=29F016 mode,
03=29F400 mode, 04=29LV800A mode
Simultaneous Operation
49h
92h
0004h
4Ah
4Bh
4Ch
94h
96h
98h
0000h
0000h
0000h
00=Not Supported, 01=Supported
Burst Mode Type
00=Not Supported, 01= Supported
Page Mode Type
00=Not Supported, 01=4 Word Page, 02= 8 Word Page
ACC (Acceleration) Supply Minimum
4Dh
4Eh
9Ah
9Ch
0000h
0000h
00=Not Supported, D7-D4: Volt, D3-D0; 100mV
ACC (Acceleration) Supply Minimum
00=Not Supported, D7-D4: Volt, D3-D0; 100mV
HARDWARE DATA PROTECTION
The command sequence requirement of unlock cycles
for programming or erasing provides data protection against
inadvertent writes (refer toTable 9 on page 21 for command
definitions). In addition, the following hardware data
protection measures prevent accidental erasure or
programming, which might otherwise be caused by
spurious system level signals during VCC power-up and
power-down transitions, or from system noise.
WRITE PULSE GLITCH PROTECTION
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
LOGICAL INHIBIT
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
LOW VCC WRITE INHIBIT
When VCC is less than VLKO, the device does not accept
any write cycles. This protects data during VCC power-up
and power-down. The command register and all internal
program/erase circuits are disabled, and the device resets.
Subsequent writes are ignored until VCC is greater than
VLKO. The system must provide the proper signals to the
control pins to prevent unintentional writes when VCC is
POWER-UP WRITE INHIBIT
If WE# = CE# = VIL and OE# = VIH during power up, the
device does not accept commands on the rising edge of
WE#. The internal state machine is automatically reset
to reading array data on power-up.
greater than VLKO
.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS29LV016J
Rev. 0.0 02/09
16
AUSTIN [ AUSTIN SEMICONDUCTOR ]
