T5743
Figure 26. Timing Characteristic of the Data Clock (Rising Edge on Pin DATA)
Data_Out
V
X
S
S
= 0,65 * V
= 0,35 * V
V Ih
Il
Serial bi-directionalV
data line
Data_In
DATA_CLK
tDelay1
tDelay
tDelay2
tP_Data_Clk
Figure 27. Timing Characteristic of the Data Clock (Falling Edge of the Pin DATA)
Data_Out
VX
VIh = 0,65 * V S
Serial bi-directional
data line
VIl = 0,35 * V S
Data_In
DATA_CLK
tDelay1
tDelay
tDelay2
tP_Data_Clk
Digital Noise
Suppression
After a data transmission, digital noise appears on the data output (see Figure 28). To
prevent that digital noise keeps the connected microcontroller busy, it can be sup-
pressed in two different ways.
Automatic Noise Suppression If the bit Noise_Disable (Table 10) in the OPMODE register is set to 1 (default), the
(see Figure 29)
receiver changes to bit-check mode at the end of a valid data stream. The digital noise
is suppressed and the level at Pin DATA is High in that case. The receiver changes
back to receiving mode, if the bit check was successful.
This way to suppress the noise is recommended if the data stream is Manchester or Bi-
phase coded and is active after power on.
Figure 30 illustrates the behavior of the data output at the end of a data stream. Note
that if the last period of the data stream is a high period (rising edge to falling edge), a
pulse occurs on Pin DATA. The length of the pulse depends on the selected baud-rate
range.
21
4569A–RKE–12/02
ATMEL [ ATMEL ]
