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MEGA128CAN 参数 Datasheet PDF下载

MEGA128CAN图片预览
型号: MEGA128CAN
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器,带有ISP功能的Flash和CAN控制器128K字节 [Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER]
分类和应用: 微控制器
文件页数/大小: 413 页 / 5507 K
品牌: ATMEL [ ATMEL ]
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Enabling and disabling of the clock input must be done when T3/T1/T0 has been stable  
for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock  
pulse is generated.  
Each half period of the external clock applied must be longer than one system clock  
cycle to ensure correct sampling. The external clock must be guaranteed to have less  
than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50 % duty cycle.  
Since the edge detector uses sampling, the maximum frequency of an external clock it  
can detect is half the sampling frequency (Nyquist sampling theorem). However, due to  
variation of the system clock frequency and duty cycle caused by Oscillator source  
(crystal, resonator, and capacitors) tolerances, it is recommended that maximum fre-  
quency of an external clock source is less than fclk_I/O/2.5.  
An external clock source can not be prescaled.  
Figure 36. Prescaler for Timer/Counter3, Timer/Counter1 and Timer/Counter0(1)  
CK  
10-BIT T/C PRESCALER  
Clear  
PSR310  
T3  
T1  
Synchronization  
Synchronization  
Synchronization  
T0  
0
0
0
CS00  
CS01  
CS02  
CS10  
CS11  
CS12  
CS30  
CS31  
CS32  
TIMER/COUNTER0 CLOCK SOURCE  
TIMER/COUNTER1 CLOCK SOURCE  
TIMER/COUNTER3 CLOCK SOURCE  
clkT0  
clkT1  
clkT3  
Note:  
1. The synchronization logic on the input pins (T0/T1/T3) is shown in Figure 35.  
Timer/Counter0/1/3  
Prescalers  
Register Description  
General Timer/Counter  
Control Register – GTCCR  
Bit  
7
TSM  
R
6
5
4
3
2
1
PSR2  
R/W  
0
0
PSR310  
R/W  
0
GTCCR  
Read/Write  
Initial Value  
R
0
R
0
R
0
R
0
R
0
0
• Bit 7 – TSM: Timer/Counter Synchronization Mode  
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this  
mode, the value that is written to the PSR2 and PSR310 bits is kept, hence keeping the  
corresponding prescaler reset signals asserted. This ensures that the corresponding  
Timer/Counters are halted and can be configured to the same value without the risk of  
one of them advancing during configuration. When the TSM bit is written to zero, the  
PSR2 and PSR310 bits are cleared by hardware, and the Timer/Counters start counting  
simultaneously.  
92  
AT90CAN128  
4250E–CAN–12/04  
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