AT90CAN128
Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer
Interrupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock
source on the T0 pin. The Clock Select logic block controls which clock source and edge
the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is
inactive when no clock source is selected. The output from the Clock Select logic is
referred to as the timer clock (clkT0).
The double buffered Output Compare Register (OCR0A) is compared with the
Timer/Counter value at all times. The result of the compare can be used by the Wave-
form Generator to generate a PWM or variable frequency output on the Output Compare
pin (OC0A). See “Output Compare Unit” on page 96 for details. The compare match
event will also set the Compare Flag (OCF0A) which can be used to generate an Output
Compare interrupt request.
Definitions
The definitions in Table 53 are also used extensively throughout the document.
Table 53. Definitions
BOTTOM The counter reaches the BOTTOM when it becomes 0x00.
MAX
TOP
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
The counter reaches the TOP when it becomes equal to the highest
value in the count sequence. The TOP value can be assigned to be the
fixed value 0xFF (MAX) or the value stored in the OCR0A Register. The
assignment is dependent on the mode of operation.
Timer/Counter Clock
Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock
source is selected by the Clock Select logic which is controlled by the Clock Select
(CS02:0) bits located in the Timer/Counter Control Register (TCCR0A). For details on
clock sources and prescaler, see “Timer/Counter3/1/0 Prescalers” on page 91.
Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
Figure 38 shows a block diagram of the counter and its surroundings.
Figure 38. Counter Unit Block Diagram
TOVn
(Int.Req.)
DATA BUS
Clock Select
count
clear
Edge
Detector
Tn
clkTn
TCNTn
Control Logic
direction
( From Prescaler )
bottom
top
Signal description (internal signals):
count Increment or decrement TCNT0 by 1.
direction Select between increment and decrement.
clear Clear TCNT0 (set all bits to zero).
95
4250E–CAN–12/04
ATMEL [ ATMEL ]
