欢迎访问ic37.com |
会员登录 免费注册
发布采购

MEGA128CAN 参数 Datasheet PDF下载

MEGA128CAN图片预览
型号: MEGA128CAN
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器,带有ISP功能的Flash和CAN控制器128K字节 [Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER]
分类和应用: 微控制器
文件页数/大小: 413 页 / 5507 K
品牌: ATMEL [ ATMEL ]
 浏览型号MEGA128CAN的Datasheet PDF文件第30页浏览型号MEGA128CAN的Datasheet PDF文件第31页浏览型号MEGA128CAN的Datasheet PDF文件第32页浏览型号MEGA128CAN的Datasheet PDF文件第33页浏览型号MEGA128CAN的Datasheet PDF文件第35页浏览型号MEGA128CAN的Datasheet PDF文件第36页浏览型号MEGA128CAN的Datasheet PDF文件第37页浏览型号MEGA128CAN的Datasheet PDF文件第38页  
System Clock  
Clock Systems and  
their Distribution  
Figure 19 presents the principal clock systems in the AVR and their distribution. All of  
the clocks need not be active at a given time. In order to reduce power consumption, the  
clocks to unused modules can be halted by using different sleep modes, as described in  
“Power Management and Sleep Modes” on page 43. The clock systems are detailed  
below.  
Figure 19. Clock Distribution  
Asynchronous  
Timer/Counter2  
CAN  
Controller  
General I/O  
Modules  
Flash and  
EEPROM  
ADC  
CPU Core  
RAM  
clkADC  
clkI/O  
clkCPU  
AVR Clock  
Control Unit  
CLKO  
clkASY  
clkFLASH  
CKOUT Fuse  
Reset Logic  
Watchdog Timer  
Source clock  
Watchdog clock  
Prescaler  
Watchdog  
Oscillator  
Clock  
Multiplexer  
Multiplexer  
Timer/Counter2  
External Clock  
Timer/Counter2  
Oscillator  
Crystal  
Oscillator  
Low-frequency  
Crystal Oscillator  
Calibrated RC  
Oscillator  
External Clock  
TOSC1  
TOSC2  
XTAL1  
XTAL2  
CPU Clock – clkCPU  
I/O Clock – clkI/O  
The CPU clock is routed to parts of the system concerned with operation of the AVR  
core. Examples of such modules are the General Purpose Register File, the Status Reg-  
ister and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the  
core from performing general operations and calculations.  
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, CAN,  
USART. The I/O clock is also used by the External Interrupt module, but note that some  
external interrupts are detected by asynchronous logic, allowing such interrupts to be  
detected even if the I/O clock is halted. Also note that address recognition in the TWI  
module is carried out asynchronously when clkI/O is halted, enabling TWI address recep-  
tion in all sleep modes.  
Flash Clock – clkFLASH  
The Flash clock controls operation of the Flash interface. The Flash clock is usually  
active simultaneously with the CPU clock.  
Asynchronous Timer Clock – The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked  
clkASY  
directly from an external clock or an external 32 kHz clock crystal. The dedicated clock  
34  
AT90CAN128  
4250E–CAN–12/04  
 复制成功!