ATmega64A
Figure 27-12. State Machine Sequence for Changing the Instruction Word
1
Test-Logic-Reset
0
1
1
1
0
Run-Test/Idle
Select-DR Scan
Select-IR Scan
0
0
Capture-IR
0
1
1
Capture-DR
0
Shift-DR
0
Shift-IR
0
1
Exit1-DR
0
1
1
1
Exit1-IR
0
Pause-IR
1
Pause-DR
1
0
0
0
0
Exit2-DR
1
Exit2-IR
1
Update-DR
Update-IR
1
1
0
0
27.9.2
AVR_RESET (0xC)
The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking
the device out from the Reset mode. The TAP controller is not reset by this instruction. The one
bit Reset Register is selected as Data Register. Note that the reset will be active as long as there
is a logic 'one' in the Reset Chain. The output from this chain is not latched.
The active states are:
• Shift-DR: The Reset Register is shifted by the TCK input.
27.9.3
PROG_ENABLE (0x4)
The AVR specific public JTAG instruction for enabling programming via the JTAG port. The 16-
bit Programming Enable Register is selected as data register. The active states are the
following:
• Shift-DR: the Programming enable signature is shifted into the data register.
315
8160C–AVR–07/09
ATMEL [ ATMEL ]
