ATmega64A
• Virtual Flash Page Load Register
• Virtual Flash Page Read Register
27.9.8
Reset Register
The Reset Register is a Test Data Register used to reset the part during programming. It is
required to reset the part before entering programming mode.
A high value in the Reset Register corresponds to pulling the External Reset low. The part is
reset as long as there is a high value present in the Reset Register. Depending on the Fuse set-
tings for the clock options, the part will remain reset for a Reset Time-out Period (refer to “Clock
Sources” on page 38) after releasing the Reset Register. The output from this data register is not
latched, so the reset will take place immediately, as shown in Figure 25-2 on page 261.
27.9.9
Programming Enable Register
The Programming Enable Register is a 16-bit register. The contents of this register is compared
to the programming enable signature, binary code 1010_0011_0111_0000. When the contents
of the register is equal to the programming enable signature, programming via the JTAG port is
enabled. The register is reset to 0 on Power-on Reset, and should always be reset when leaving
Programming mode.
Figure 27-13. Programming Enable Register
TDI
$A370
D
D
Q
A
T
A
Programming Enable
=
ClockDR & PROG_ENABLE
TDO
27.9.10 Programming Command Register
The Programming Command Register is a 15-bit register. This register is used to serially shift in
programming commands, and to serially shift out the result of the previous command, if any. The
JTAG Programming Instruction Set is shown in Table 27-16. The state sequence when shifting
in the programming commands is illustrated in Figure 27-15.
317
8160C–AVR–07/09
ATMEL [ ATMEL ]
