ATmega64A
15.11.9 OCR1AH and OCR1AL –Output Compare Register 1 A
Bit
7
6
5
4
3
2
1
0
0x2B (0x4B)
0x2A (0x4A)
Read/Write
Initial Value
OCR1A[15:8]
OCR1A[7:0]
OCR1AH
OCR1AL
R/W
0
R/W
0
R/W
0
R/W
R/W
R/W
0
R/W
0
R/W
0
0
0
15.11.10 OCR1BH and OCR1BL – Output Compare Register 1 B
Bit
7
6
5
4
3
2
1
0
0x29 (0x49)
0x28 (0x48)
Read/Write
Initial Value
OCR1B[15:8]
OCR1B[7:0]
OCR1BH
OCR1BL
R/W
0
R/W
0
R/W
0
R/W
R/W
R/W
0
R/W
0
R/W
0
0
0
15.11.11 OCR1CH and OCR1CL – Output Compare Register 1 C
Bit
7
6
5
4
3
2
1
0
(0x79)
OCR1C[15:8]
OCR1C[7:0]
OCR1CH
OCR1CL
(0x78)
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
R/W
R/W
0
R/W
0
R/W
0
0
0
15.11.12 OCR3AH and OCR3AL – Output Compare Register 3 A
Bit
7
6
5
4
3
2
1
0
(0x87)
OCR3A[15:8]
OCR3A[7:0]
OCR3AH
OCR3AL
(0x86)
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
R/W
R/W
0
R/W
0
R/W
0
0
0
15.11.13 OCR3BH and OCR3BL – Output Compare Register 3 B
Bit
7
6
5
4
3
2
1
0
(0x85)
OCR3B[15:8]
OCR3B[7:0]
OCR3BH
OCR3BL
(0x84)
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
R/W
R/W
0
R/W
0
R/W
0
0
0
15.11.14 OCR3CH and OCR3CL – Output Compare Register 3 C
Bit
7
6
5
4
3
2
1
0
(0x83)
OCR3C[15:8]
OCR3C[7:0]
OCR3CH
OCR3CL
(0x82)
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
R/W
R/W
0
R/W
0
R/W
0
0
0
The Output Compare Registers contain a 16-bit value that is continuously compared with the
counter value (TCNTn). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OCnx pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are
written simultaneously when the CPU writes to these registers, the access is performed using an
8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-
bit registers. See “Accessing 16-bit Registers” on page 114.
138
8160C–AVR–07/09
ATMEL [ ATMEL ]
