ATmega64A
15.11.15 ICR1H and ICR1L – Input Capture Register 1
Bit
7
6
5
4
3
2
1
0
0x27 (0x47)
0x26 (0x46)
Read/Write
Initial Value
ICR1[15:8]
ICR1[7:0]
ICR1H
ICR1L
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15.11.16 ICR3H and ICR3L – Input Capture Register 3
Bit
7
6
5
4
3
2
1
0
(0x81)
ICR3[15:8]
ICR3[7:0]
ICR3H
ICR3L
(0x80)
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
R/W
0
R/W
0
R/W
0
R/W
0
0
The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the
ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit
registers. See “Accessing 16-bit Registers” on page 114.
15.11.17 TIMSK – Timer/Counter Interrupt Mask Register(1)
Bit
0x37 (0x57)
7
6
5
4
OCIE1A
R/W
0
3
OCIE1B
R/W
0
2
TOIE1
R/W
0
1
OCIE0
R/W
0
0
TOIE0
R/W
0
OCIE2
TOIE2
TICIE1
TIMSK
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
Note:
1. This register contains interrupt control bits for several Timer/Counters, but only Timer1 bits are
described in this section. The remaining bits are described in their respective timer sections.
• Bit 5 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt
Vector (see “Interrupts” on page 60) is executed when the ICF1 flag, located in TIFR, is set.
• Bit 4 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 60) is executed when the OCF1A flag, located in TIFR,
is set.
• Bit 3 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 60) is executed when the OCF1B flag, located in TIFR,
is set.
139
8160C–AVR–07/09
ATMEL [ ATMEL ]
