ATmega16/32/64/M1/C1
14.6.1
Value Update Synchronization
New timing values or PSC output configuration can be written during the PSC cycle. Thanks to
LOCK configuration bit, the new whole set of values can be taken into account after the end of
the PSC cycle.
When LOCK configuration bit is set, there is no update. The update of the PSC internal registers
will be done at the end of the PSC cycle if the LOCK bit is released to zero.
The registers which update is synchronized thanks to LOCK are POC, POM2, POCRnSAH/L,
POCRnRAH/L, POCRnSBH/L and POCRnRBH/L.
See these register’s description starting on page 153.
See “PSC Configuration Register – PCNF” on page 153.
14.7 Overlap Protection
Thanks to Overlap Protection two outputs on a same module cannot be active at the same time.
So it cannot generate cross conduction. This feature can be disactivated thanks to POVEn (PSC
Overlap Enable).
For ATmega16/64M1, and ATmega32M1 since rev C, the overlap protection is activated with
only one condition:
1. POVENn=0 (PSC Module n Overlap Enable)
Up to rev B of ATmega32M1, the overlap protection was activated with the 2 following
conditions:
2. POVENn=0 (PSC Module n Overlap Enable)
3. The two channels A and B of a pwm pair n must be activated (POENnA=POENnB= 1)
This difference can induce some behavior change between rev B & rev C of ATmega32M1,
when only one channel of a PWM pair output is active.
To avoid such behavior, it is recommended in case of using only one channel of a pwm pair, to
disable Overlap protection bit (POVENn =1).
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7647F–AVR–04/09
ATMEL [ ATMEL ]
