ATmega16/32/64/M1/C1
Figure 14-5. Controlled Start and Stop Mechanism in One-Ramp Mode
POCRnRB
POCRnSB
POCRnRA
POCRnSA
PSC Counter
0
Run
PSCOUTnA
PSCOUTnB
Note:
See “PSC Control Register – PCTL” on page 154. (PCCYC = 1)
14.5.3.2
Center Aligned Mode
In center aligned mode, the center of PSCOUTnA and PSCOUTnB signals are centered.
Figure 14-6. PSCOUTnA & PSCOUTnB Basic Waveforms in Center Aligned Mode
PSC Counter
POCRnRB
POCRnSB
POCRnSA
0
On-Time 0
On-Time 1
On-Time 1
PSCOUTnA
PSCOUTnB
Dead-Time
Dead-Time
PSC Cycle
On-Time 0 = 2 * POCRnSAH/L * 1/Fclkpsc
On-Time 1 = 2 * (POCRnRBH/L - POCRnSBH/L + 1) * 1/Fclkpsc
Dead-Time = (POCRnSBH/L - POCRnSAH/L) * 1/Fclkpsc
PSC Cycle = 2 * (POCRnRBH/L + 1) * 1/Fclkpsc
Minimal value for PSC Cycle = 2 * 1/Fclkpsc
141
7647F–AVR–04/09
ATMEL [ ATMEL ]
