ATmega16/32/64/M1/C1
Figure 14-3. Cycle Presentation in Centered Mode
One PSC Cycle
PSC Counter Value
UPDATE
Figure 14-2 and Figure 14-3 graphically illustrate the values held in the PSC counter. Centered
Mode is like One Ramp Mode which counts down and then up.
Notice that the update of the waveform generator registers is done regardless of ramp Mode at
the end of the PSC cycle.
14.5.3
Operation Mode Descriptions
Waveforms and duration of output signals are determined by parameters held in the registers
(POCRnSA, POCRnRA, POCRnSB, POCR_RB) and by the running mode. Two modes are pos-
sible :
• One Ramp Mode. In this mode, all the 3 PSCOUTnB outputs are edge-aligned and the 3
PSCOUTnA can be also edge-aligned when setting the same values in the dedicated
registers.
In this mode, the PWM frequency is twice the Center Aligned Mode PWM frequency.
• Center Aligned Mode. In this mode, all the 6 PSC outputs are aligned at the center of the
period. Except when using the same duty cycles on the 3 modules, the edges of the outputs
are not aligned. So the PSC outputs do not commute at the same time, thus the system
which is driven by these outputs will generate less commutation noise.
In this mode, the PWM frequency is twice slower than in One Ramp Mode.
14.5.3.1
One Ramp Mode (Edge-Aligned)
The following figure shows the resultant outputs PSCOUTnA and PSCOUTnB operating in one
ramp mode over a PSC cycle.
139
7647F–AVR–04/09
ATMEL [ ATMEL ]
