ATmega16/32/64/M1/C1
Figure 14-11. PSC Input Filterring
CLK
PSC
Digital
PSC Module n Input
Filter
4 x CLK
PSC
PSC Input
Module X
Ouput
Stage
PSCOUTnX
PIN
14.9.1.2
Signal Polarity
One can select the active edge (edge modes) or the active level (level modes) See PELEVnx bit
description in Section "PSC Module n Input Control Register – PMICn", page 155.
If PELEVnx bit set, the significant edge of PSCn Input A or B is rising (edge modes) or the active
level is high (level modes) and vice versa for unset/falling/low
• In 2- or 4-ramp mode, PSCn Input A is taken into account only during Dead-Time0 and
On-Time0 period (respectively Dead-Time1 and On-Time1 for PSCn Input B).
• In 1-ramp-mode PSC Input A or PSC Input B act on the whole ramp.
14.9.1.3
Input Mode Operation
Thanks to 4 configuration bits (PRFM3:0), it’s possible to define the mode of the PSC inputs.
Table 14-5. PSC Input Mode Operation
PRFMn2:0
000b
Description
No action, PSC Input is ignored
Disactivate module n Outputs A
Disactivate module n Output B
Disactivate module n Output A & B
Disactivate all PSC Output
001b
010b
011b
10x
11xb
Halt PSC and Wait for Software Action
Notice: All following examples are given with rising edge or high level active inputs.
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7647F–AVR–04/09
ATMEL [ ATMEL ]
