Note that in center aligned mode, POCRnRAH/L is not required (as it is in one-ramp mode) to
control PSC Output waveform timing. This allows POCRnRAH/L to be freely used to adjust ADC
synchronization (See “Analog Synchronization” on page 149.).
Figure 14-7. Controlled Start and Stop Mechanism in Centered Mode
POCRnRB
POCRnSB
POCRnSA
PSC Counter
0
Run
PSCOUTnA
PSCOUTnB
Note:
See “PSC Control Register – PCTL” on page 154.(PCCYC = 1)
14.6 Update of Values
To avoid unasynchronous and incoherent values in a cycle, if an update of one of several values
is necessary, all values are updated at the same time at the end of the cycle by the PSC. The
new set of values is calculated by sofware and the update is initiated by software.
Figure 14-8. Update at the end of complete PSC cycle.
Regulation Loop
Calculation
Writting in
PSC Registers
Request for
an Update
Software
Cycle
With Set i
Cycle
With Set i
Cycle
With Set i
Cycle
With Set i
PSC
Cycle
With Set j
End of Cycle
The software can stop the cycle before the end to update the values and restart a new PSC
cycle.
142
ATmega16/32/64/M1/C1
7647F–AVR–04/09
ATMEL [ ATMEL ]
