(WGM13:0 = 9). The counter has then reached the TOP and changes the count
direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing
diagram for the phase correct and frequency correct PWM mode is shown on Figure 40.
The figure shows phase and frequency correct PWM mode when OCR1A or ICR1 is
used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for
illustrating the dual-slope operation. The diagram includes non-inverted and inverted
PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare
matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a
Compare Match occurs.
Figure 40. Phase and Frequency Correct PWM Mode, Timing Diagram
OCnA Interrupt Flag Set or
ICFn Interrupt Flag Set
(Interrupt on TOP)
OCRnx / TOP Update and
TOVn Interrupt Flag Set
(Interrupt on Bottom)
TCNTn
(COMnx1:0 = 2)
OCnx
(COMnx1:0 = 3)
OCnx
1
2
3
4
Period
The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the
OCR1x Registers are updated with the double buffer value (at BOTTOM). When either
OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag set when
TCNT1 has reached TOP. The Interrupt Flags can then be used to generate an interrupt
each time the counter reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is
higher or equal to the value of all of the Compare Registers. If the TOP value is lower
than any of the Compare Registers, a Compare Match will never occur between the
TCNT1 and the OCR1x.
As Figure 40 shows the output generated is, in contrast to the Phase Correct mode,
symmetrical in all periods. Since the OCR1x Registers are updated at BOTTOM, the
length of the rising and the falling slopes will always be equal. This gives symmetrical
output pulses and is therefore frequency correct.
Using the ICR1 Register for defining TOP works well when using fixed TOP values. By
using ICR1, the OCR1A Register is free to be used for generating a PWM output on
OC1A. However, if the base PWM frequency is actively changed by changing the TOP
value, using the OCR1A as TOP is clearly a better choice due to its double buffer
feature.
In phase and frequency correct PWM mode, the compare units allow generation of
PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to 2 will produce a non-
inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0
92
ATmega8(L)
2486M–AVR–12/03
ATMEL [ ATMEL ]
