Table 37 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the
fast PWM mode.
Table 37. Compare Output Mode, Fast PWM(1)
COM1A1/
COM1B1
COM1A0/
COM1B0
Description
0
0
0
1
Normal port operation, OC1A/OC1B disconnected.
WGM13:0 = 15: Toggle OC1A on Compare Match, OC1B
disconnected (normal port operation). For all other WGM1
settings, normal port operation, OC1A/OC1B disconnected.
1
1
0
1
Clear OC1A/OC1B on Compare Match, set OC1A/OC1B at TOP
Set OC1A/OC1B on Compare Match, clear OC1A/OC1B at TOP
Note:
1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is
set. In this case the Compare Match is ignored, but the set or clear is done at TOP.
See “Fast PWM Mode” on page 87. for more details.
Table 38 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the
phase correct or the phase and frequency correct, PWM mode.
Table 38. Compare Output Mode, Phase Correct and Phase and Frequency Correct
PWM(1)
COM1A1/
COM1B1
COM1A0/
COM1B0
Description
0
0
0
1
Normal port operation, OC1A/OC1B disconnected.
WGM13:0 = 9 or 14: Toggle OC1A on Compare Match, OC1B
disconnected (normal port operation). For all other WGM1
settings, normal port operation, OC1A/OC1B disconnected.
1
1
0
1
Clear OC1A/OC1B on Compare Match when up-counting. Set
OC1A/OC1B on Compare Match when downcounting.
Set OC1A/OC1B on Compare Match when up-counting. Clear
OC1A/OC1B on Compare Match when downcounting.
Note:
1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is
set. See “Phase Correct PWM Mode” on page 89. for more details.
• Bit 3 – FOC1A: Force Output Compare for channel A
• Bit 2 – FOC1B: Force Output Compare for channel B
The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM
mode. However, for ensuring compatibility with future devices, these bits must be set to
zero when TCCR1A is written when operating in a PWM mode. When writing a logical
one to the FOC1A/FOC1B bit, an immediate Compare Match is forced on the waveform
generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits set-
ting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the
value present in the COM1x1:0 bits that determine the effect of the forced compare.
A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear
Timer on Compare Match (CTC) mode using OCR1A as TOP.
The FOC1A/FOC1B bits are always read as zero.
• Bit 1:0 – WGM11:0: Waveform Generation Mode
Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the
counting sequence of the counter, the source for maximum (TOP) counter value, and
96
ATmega8(L)
2486M–AVR–12/03
ATMEL [ ATMEL ]
