ATmega8(L)
period will differ in length. The difference in length gives the unsymmetrical result on the
output.
It is recommended to use the Phase and Frequency Correct mode instead of the Phase
Correct mode when changing the TOP value while the Timer/Counter is running. When
using a static TOP value there are practically no differences between the two modes of
operation.
In phase correct PWM mode, the compare units allow generation of PWM waveforms on
the OC1x pins. Setting the COM1x1:0 bits to 2 will produce a non-inverted PWM and an
inverted PWM output can be generated by setting the COM1x1:0 to 3. See Table 38 on
page 96. The actual OC1x value will only be visible on the port pin if the data direction
for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by set-
ting (or clearing) the OC1x Register at the Compare Match between OCR1x and TCNT1
when the counter increments, and clearing (or setting) the OC1x Register at Compare
Match between OCR1x and TCNT1 when the counter decrements. The PWM frequency
for the output when using phase correct PWM can be calculated by the following
equation:
f
clk_I/O
f
= ---------------------------
OCnxPCPWM
2 N TOP
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represent special cases when generating a
PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to
BOTTOM the output will be continuously low and if set equal to TOP the output will be
continuously high for non-inverted PWM mode. For inverted PWM the output will have
the opposite logic values.
If OCR1A is used to define the TOP value (WMG13:0 = 11) and COM1A1:0 = 1, the
OC1A output will toggle with a 50% duty cycle.
Phase and Frequency Correct The phase and frequency correct Pulse Width Modulation, or phase and frequency cor-
PWM Mode
rect PWM mode (WGM13:0 = 8 or 9) provides a high resolution phase and frequency
correct PWM waveform generation option. The phase and frequency correct PWM
mode is, like the phase correct PWM mode, based on a dual-slope operation. The
counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOT-
TOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared
on the Compare Match between TCNT1 and OCR1x while upcounting, and set on the
Compare Match while downcounting. In inverting Compare Output mode, the operation
is inverted. The dual-slope operation gives a lower maximum operation frequency com-
pared to the single-slope operation. However, due to the symmetric feature of the dual-
slope PWM modes, these modes are preferred for motor control applications.
The main difference between the phase correct, and the phase and frequency correct
PWM mode is the time the OCR1x Register is updated by the OCR1x Buffer Register,
(see Figure 39 and Figure 40).
The PWM resolution for the phase and frequency correct PWM mode can be defined by
either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to
0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM
resolution in bits can be calculated using the following equation:
log(TOP + 1)
R
= ----------------------------------
PFCPWM
log(2)
In phase and frequency correct PWM mode the counter is incremented until the counter
value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A
91
2486M–AVR–12/03
ATMEL [ ATMEL ]
