欢迎访问ic37.com |
会员登录 免费注册
发布采购

ATMEGA48PA-CCU 参数 Datasheet PDF下载

ATMEGA48PA-CCU图片预览
型号: ATMEGA48PA-CCU
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 20MHz, CMOS, PBGA32, 4 X 4 MM, 0.60 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, UFBGA-32]
分类和应用: 闪存微控制器
文件页数/大小: 349 页 / 2752 K
品牌: ATMEL [ ATMEL ]
 浏览型号ATMEGA48PA-CCU的Datasheet PDF文件第93页浏览型号ATMEGA48PA-CCU的Datasheet PDF文件第94页浏览型号ATMEGA48PA-CCU的Datasheet PDF文件第95页浏览型号ATMEGA48PA-CCU的Datasheet PDF文件第96页浏览型号ATMEGA48PA-CCU的Datasheet PDF文件第98页浏览型号ATMEGA48PA-CCU的Datasheet PDF文件第99页浏览型号ATMEGA48PA-CCU的Datasheet PDF文件第100页浏览型号ATMEGA48PA-CCU的Datasheet PDF文件第101页  
ATmega48/88/168  
Table 49 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to fast  
PWM mode.  
Table 49. Compare Output Mode, Fast PWM Mode(1)  
COM0B1  
COM0B0  
Description  
0
0
1
1
0
1
0
1
Normal port operation, OC0B disconnected.  
Reserved  
Clear OC0B on Compare Match, set OC0B at TOP  
Set OC0B on Compare Match, clear OC0B at TOP  
Note:  
1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case,  
the Compare Match is ignored, but the set or clear is done at TOP. See “Fast PWM  
Mode” on page 91 for more details.  
Table 50 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to  
phase correct PWM mode.  
Table 50. Compare Output Mode, Phase Correct PWM Mode(1)  
COM0B1  
COM0B0  
Description  
0
0
1
0
1
0
Normal port operation, OC0B disconnected.  
Reserved  
Clear OC0B on Compare Match when up-counting. Set OC0B on  
Compare Match when down-counting.  
1
1
Set OC0B on Compare Match when up-counting. Clear OC0B on  
Compare Match when down-counting.  
Note:  
1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case,  
the Compare Match is ignored, but the set or clear is done at TOP. See “Phase Cor-  
rect PWM Mode” on page 92 for more details.  
• Bits 3, 2 – Res: Reserved Bits  
These bits are reserved bits in the ATmega48/88/168 and will always read as zero.  
• Bits 1:0 – WGM01:0: Waveform Generation Mode  
Combined with the WGM02 bit found in the TCCR0B Register, these bits control the  
counting sequence of the counter, the source for maximum (TOP) counter value, and  
what type of waveform generation to be used, see Table 51. Modes of operation sup-  
ported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare  
Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see  
“Modes of Operation” on page 90).  
Table 51. Waveform Generation Mode Bit Description  
Timer/Count  
er Mode of  
Update of  
OCRx at  
TOV Flag  
Mode WGM02 WGM01 WGM00 Operation  
TOP  
0xFF  
0xFF  
Set on(1)(2)  
0
1
0
0
0
0
0
1
Normal  
Immediate  
TOP  
MAX  
PWM, Phase  
Correct  
BOTTOM  
2
3
0
0
1
1
0
1
CTC  
OCRA Immediate  
0xFF TOP  
MAX  
MAX  
Fast PWM  
97  
2545D–AVR–07/04  
 复制成功!