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ATMEGA48PA-CCU 参数 Datasheet PDF下载

ATMEGA48PA-CCU图片预览
型号: ATMEGA48PA-CCU
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 20MHz, CMOS, PBGA32, 4 X 4 MM, 0.60 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, UFBGA-32]
分类和应用: 闪存微控制器
文件页数/大小: 349 页 / 2752 K
品牌: ATMEL [ ATMEL ]
 浏览型号ATMEGA48PA-CCU的Datasheet PDF文件第94页浏览型号ATMEGA48PA-CCU的Datasheet PDF文件第95页浏览型号ATMEGA48PA-CCU的Datasheet PDF文件第96页浏览型号ATMEGA48PA-CCU的Datasheet PDF文件第97页浏览型号ATMEGA48PA-CCU的Datasheet PDF文件第99页浏览型号ATMEGA48PA-CCU的Datasheet PDF文件第100页浏览型号ATMEGA48PA-CCU的Datasheet PDF文件第101页浏览型号ATMEGA48PA-CCU的Datasheet PDF文件第102页  
Table 51. Waveform Generation Mode Bit Description (Continued)  
Timer/Count  
er Mode of  
Update of  
OCRx at  
TOV Flag  
Mode WGM02 WGM01 WGM00 Operation  
TOP  
Set on(1)(2)  
4
5
1
1
0
0
0
1
Reserved  
PWM, Phase  
Correct  
OCRA  
TOP  
BOTTOM  
6
7
1
1
1
1
0
1
Reserved  
Fast PWM  
OCRA  
TOP  
TOP  
Notes: 1. MAX  
= 0xFF  
2. BOTTOM = 0x00  
Timer/Counter Control  
Register B – TCCR0B  
Bit  
7
FOC0A  
W
6
FOC0B  
W
5
4
3
2
CS02  
R
1
CS01  
R/W  
0
0
WGM02  
CS00  
R/W  
0
TCCR0B  
Read/Write  
Initial Value  
R
0
R
0
R
0
0
0
0
• Bit 7 – FOC0A: Force Output Compare A  
The FOC0A bit is only active when the WGM bits specify a non-PWM mode.  
However, for ensuring compatibility with future devices, this bit must be set to zero when  
TCCR0B is written when operating in PWM mode. When writing a logical one to the  
FOC0A bit, an immediate Compare Match is forced on the Waveform Generation unit.  
The OC0A output is changed according to its COM0A1:0 bits setting. Note that the  
FOC0A bit is implemented as a strobe. Therefore it is the value present in the  
COM0A1:0 bits that determines the effect of the forced compare.  
A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode  
using OCR0A as TOP.  
The FOC0A bit is always read as zero.  
• Bit 6 – FOC0B: Force Output Compare B  
The FOC0B bit is only active when the WGM bits specify a non-PWM mode.  
However, for ensuring compatibility with future devices, this bit must be set to zero when  
TCCR0B is written when operating in PWM mode. When writing a logical one to the  
FOC0B bit, an immediate Compare Match is forced on the Waveform Generation unit.  
The OC0B output is changed according to its COM0B1:0 bits setting. Note that the  
FOC0B bit is implemented as a strobe. Therefore it is the value present in the  
COM0B1:0 bits that determines the effect of the forced compare.  
A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode  
using OCR0B as TOP.  
The FOC0B bit is always read as zero.  
• Bits 5:4 – Res: Reserved Bits  
These bits are reserved bits in the ATmega48/88/168 and will always read as zero.  
• Bit 3 – WGM02: Waveform Generation Mode  
See the description in the “Timer/Counter Control Register A – TCCR0A” on page 95.  
98  
ATmega48/88/168  
2545D–AVR–07/04  
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