External Interrupt Flag
Register – EIFR
Bit
7
–
6
–
5
–
4
–
3
–
2
–
1
INTF1
R/W
0
0
INTF0
R/W
0
EIFR
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R
0
R
0
• Bit 7..2 – Res: Reserved Bits
These bits are unused bits in the ATmega48/88/168, and will always read as zero.
• Bit 1 – INTF1: External Interrupt Flag 1
When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1
becomes set (one). If the I-bit in SREG and the INT1 bit in EIMSK are set (one), the
MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter-
rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to
it. This flag is always cleared when INT1 is configured as a level interrupt.
• Bit 0 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0
becomes set (one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the
MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter-
rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to
it. This flag is always cleared when INT0 is configured as a level interrupt.
Pin Change Interrupt Control
Register - PCICR
Bit
7
–
6
–
5
–
4
–
3
–
2
PCIE2
R/W
0
1
PCIE1
R/W
0
0
PCIE0
R/W
0
PCICR
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R
0
• Bit 7..3 - Res: Reserved Bits
These bits are unused bits in the ATmega48/88/168, and will always read as zero.
• Bit 2 - PCIE2: Pin Change Interrupt Enable 2
When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
pin change interrupt 2 is enabled. Any change on any enabled PCINT23..16 pin will
cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is exe-
cuted from the PCI2 Interrupt Vector. PCINT23..16 pins are enabled individually by the
PCMSK2 Register.
• Bit 1 - PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
pin change interrupt 1 is enabled. Any change on any enabled PCINT14..8 pin will
cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is exe-
cuted from the PCI1 Interrupt Vector. PCINT14..8 pins are enabled individually by the
PCMSK1 Register.
• Bit 0 - PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
pin change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause
an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed
from the PCI0 Interrupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0
Register.
82
ATmega48/88/168
2545D–AVR–07/04
ATMEL [ ATMEL ]
