ATmega48/88/168
Analog-to-Digital
Converter
Features
• 10-bit Resolution
• 0.5 LSB Integral Non-linearity
•
2 LSB Absolute Accuracy
• 13 - 260 µs Conversion Time
• Up to 15 kSPS at Maximum Resolution
• 6 Multiplexed Single Ended Input Channels
• 2 Additional Multiplexed Single Ended Input Channels (TQFP and MLF Package only)
• Optional Left Adjustment for ADC Result Readout
• 0 - VCC ADC Input Voltage Range
• Selectable 1.1V ADC Reference Voltage
• Free Running or Single Conversion Mode
• Interrupt on ADC Conversion Complete
• Sleep Mode Noise Canceler
The ATmega48/88/168 features a 10-bit successive approximation ADC. The ADC is
connected to an 8-channel Analog Multiplexer which allows eight single-ended voltage
inputs constructed from the pins of Port A. The single-ended voltage inputs refer to 0V
(GND).
The ADC contains a Sample and Hold circuit which ensures that the input voltage to the
ADC is held at a constant level during conversion. A block diagram of the ADC is shown
in Figure 101.
The ADC has a separate analog supply voltage pin, AVCC. AVCC must not differ more
than 0.3V from VCC. See the paragraph “ADC Noise Canceler” on page 237 on how to
connect this pin.
Internal reference voltages of nominally 1.1V or AVCC are provided On-chip. The voltage
reference may be externally decoupled at the AREF pin by a capacitor for better noise
performance.
The Power Reduction ADC bit, PRADC, in “Power Reduction Register - PRR” on page
37 must be disabled by writing a logical zero to enable the ADC.
231
2545D–AVR–07/04
ATMEL [ ATMEL ]
