欢迎访问ic37.com |
会员登录 免费注册
发布采购

ATMEGA48PA-CCU 参数 Datasheet PDF下载

ATMEGA48PA-CCU图片预览
型号: ATMEGA48PA-CCU
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 20MHz, CMOS, PBGA32, 4 X 4 MM, 0.60 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, UFBGA-32]
分类和应用: 闪存微控制器
文件页数/大小: 349 页 / 2752 K
品牌: ATMEL [ ATMEL ]
 浏览型号ATMEGA48PA-CCU的Datasheet PDF文件第224页浏览型号ATMEGA48PA-CCU的Datasheet PDF文件第225页浏览型号ATMEGA48PA-CCU的Datasheet PDF文件第226页浏览型号ATMEGA48PA-CCU的Datasheet PDF文件第227页浏览型号ATMEGA48PA-CCU的Datasheet PDF文件第229页浏览型号ATMEGA48PA-CCU的Datasheet PDF文件第230页浏览型号ATMEGA48PA-CCU的Datasheet PDF文件第231页浏览型号ATMEGA48PA-CCU的Datasheet PDF文件第232页  
Analog Comparator  
The Analog Comparator compares the input values on the positive pin AIN0 and nega-  
tive pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on  
the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator’s  
output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the  
comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The  
user can select Interrupt triggering on comparator output rise, fall or toggle. A block dia-  
gram of the comparator and its surrounding logic is shown in Figure 100.  
The Power Reduction ADC bit, PRADC, in “Power Reduction Register - PRR” on page  
37 must be disabled by writing a logical zero to be able to use the ADC input MUX.  
Figure 100. Analog Comparator Block Diagram(2)  
BANDGAP  
REFERENCE  
ACBG  
ACME  
ADEN  
ADC MULTIPLEXER  
OUTPUT(1)  
Notes: 1. See Table 97 on page 230.  
2. Refer to Figure 1 on page 2 and Table 39 on page 75 for Analog Comparator pin  
placement.  
ADC Control and Status  
Register B – ADCSRB  
Bit  
7
6
ACME  
R/W  
0
5
4
3
2
ADTS2  
R/W  
0
1
ADTS1  
R/W  
0
0
ADTS0  
R/W  
0
ADCSRB  
Read/Write  
Initial Value  
R
0
R
0
R
0
R
0
• Bit 6 – ACME: Analog Comparator Multiplexer Enable  
When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is  
zero), the ADC multiplexer selects the negative input to the Analog Comparator. When  
this bit is written logic zero, AIN1 is applied to the negative input of the Analog Compar-  
ator. For a detailed description of this bit, see “Analog Comparator Multiplexed Input” on  
page 230.  
Analog Comparator Control  
and Status Register – ACSR  
Bit  
7
6
ACBG  
R/W  
0
5
ACO  
R
4
ACI  
R/W  
0
3
ACIE  
R/W  
0
2
ACIC  
R/W  
0
1
ACIS1  
R/W  
0
0
ACIS0  
R/W  
0
ACD  
R/W  
0
ACSR  
Read/Write  
Initial Value  
N/A  
• Bit 7 – ACD: Analog Comparator Disable  
When this bit is written logic one, the power to the Analog Comparator is switched off.  
This bit can be set at any time to turn off the Analog Comparator. This will reduce power  
consumption in Active and Idle mode. When changing the ACD bit, the Analog Compar-  
228  
ATmega48/88/168  
2545D–AVR–07/04  
 复制成功!