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ATMEGA48PA-CCU 参数 Datasheet PDF下载

ATMEGA48PA-CCU图片预览
型号: ATMEGA48PA-CCU
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, AVR RISC CPU, 20MHz, CMOS, PBGA32, 4 X 4 MM, 0.60 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, UFBGA-32]
分类和应用: 闪存微控制器
文件页数/大小: 349 页 / 2752 K
品牌: ATMEL [ ATMEL ]
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ATmega48/88/168  
After initialization the USART is ready for doing data transfers. A data transfer is initiated  
by writing to the UDRn I/O location. This is the case for both sending and receiving data  
since the transmitter controls the transfer clock. The data written to UDRn is moved from  
the transmit buffer to the shift register when the shift register is ready to send a new  
frame.  
Note:  
To keep the input buffer in sync with the number of data bytes transmitted, the UDRn reg-  
ister must be read once for each byte transmitted. The input buffer operation is identical  
to normal USART mode, i.e. if an overflow occurs the character last received will be lost,  
not the first data in the buffer. This means that if four bytes are transferred, byte 1 first,  
then byte 2, 3, and 4, and the UDRn is not read before all transfers are completed, then  
byte 3 to be received will be lost, and not byte 1.  
The following code examples show a simple USART in MSPIM mode transfer function  
based on polling of the Data Register Empty (UDREn) Flag and the Receive Complete  
(RXCn) Flag. The USART has to be initialized before the function can be used. For the  
assembly code, the data to be sent is assumed to be stored in Register R16 and the  
data received will be available in the same register (R16) after the function returns.  
The function simply waits for the transmit buffer to be empty by checking the UDREn  
Flag, before loading it with new data to be transmitted. The function then waits for data  
to be present in the receive buffer by checking the RXCn Flag, before reading the buffer  
and returning the value.  
193  
2545D–AVR–07/04  
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