ATmega48/88/168
USART MSPIM Control and
Status Register n A - UCSRnA
•
Bit
7
RXCn
R/W
0
6
TXCn
R/W
0
5
UDREn
R/W
0
4
-
3
-
2
-
1
-
0
-
UCSRnA
Read/Write
Initial Value
R
0
R
0
R
1
R
1
R
0
• Bit 7 - RXCn: USART Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when the
receive buffer is empty (i.e., does not contain any unread data). If the Receiver is dis-
abled, the receive buffer will be flushed and consequently the RXCn bit will become
zero. The RXCn Flag can be used to generate a Receive Complete interrupt (see
description of the RXCIEn bit).
• Bit 6 - TXCn: USART Transmit Complete
This flag bit is set when the entire frame in the Transmit Shift Register has been shifted
out and there are no new data currently present in the transmit buffer (UDRn). The
TXCn Flag bit is automatically cleared when a transmit complete interrupt is executed,
or it can be cleared by writing a one to its bit location. The TXCn Flag can generate a
Transmit Complete interrupt (see description of the TXCIEn bit).
• Bit 5 - UDREn: USART Data Register Empty
The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If
UDREn is one, the buffer is empty, and therefore ready to be written. The UDREn Flag
can generate a Data Register Empty interrupt (see description of the UDRIE bit).
UDREn is set after a reset to indicate that the Transmitter is ready.
• Bit 4:0 - Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future
devices, these bits must be written to zero when UCSRnA is written.
USART MSPIM Control and
Status Register n B - UCSRnB
Bit
7
RXCIEn
R/W
0
6
TXCIEn
R/W
0
5
UDRIE
R/W
0
4
RXENn
R/W
0
3
TXENn
R/W
0
2
-
1
-
0
-
UCSRnB
Read/Write
Initial Value
R
1
R
1
R
0
• Bit 7 - RXCIEn: RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete
interrupt will be generated only if the RXCIEn bit is written to one, the Global Interrupt
Flag in SREG is written to one and the RXCn bit in UCSRnA is set.
• Bit 6 - TXCIEn: TX Complete Interrupt Enable
Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete
interrupt will be generated only if the TXCIEn bit is written to one, the Global Interrupt
Flag in SREG is written to one and the TXCn bit in UCSRnA is set.
• Bit 5 - UDRIE: USART Data Register Empty Interrupt Enable
Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty
interrupt will be generated only if the UDRIE bit is written to one, the Global Interrupt
Flag in SREG is written to one and the UDREn bit in UCSRnA is set.
• Bit 4 - RXENn: Receiver Enable
Writing this bit to one enables the USART Receiver in MSPIM mode. The Receiver will
override normal port operation for the RxDn pin when enabled. Disabling the Receiver
will flush the receive buffer. Only enabling the receiver in MSPI mode (i.e. setting
195
2545D–AVR–07/04
ATMEL [ ATMEL ]
