RXENn=1 and TXENn=0) has no meaning since it is the transmitter that controls the
transfer clock and since only master mode is supported.
• Bit 3 - TXENn: Transmitter Enable
Writing this bit to one enables the USART Transmitter. The Transmitter will override nor-
mal port operation for the TxDn pin when enabled. The disabling of the Transmitter
(writing TXENn to zero) will not become effective until ongoing and pending transmis-
sions are completed, i.e., when the Transmit Shift Register and Transmit Buffer Register
do not contain data to be transmitted. When disabled, the Transmitter will no longer
override the TxDn port.
• Bit 2:0 - Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future
devices, these bits must be written to zero when UCSRnB is written.
USART MSPIM Control and
Status Register n C - UCSRnC
Bit
7
UMSELn1
R/W
6
UMSELn0
R/W
5
-
4
-
3
-
2
UDORDn
R/W
1
UCPHAn
R/W
0
UCPOLn
R/W
UCSRnC
Read/Write
Initial Value
R
0
R
0
R
0
0
0
1
1
0
• Bit 7:6 - UMSELn1:0: USART Mode Select
These bits select the mode of operation of the USART as shown in Table 87. See
“USART Control and Status Register n C – UCSRnC” on page 183 for full description of
the normal USART operation. The MSPIM is enabled when both UMSELn bits are set to
one. The UDORDn, UCPHAn, and UCPOLn can be set in the same write operation
where the MSPIM is enabled.
Table 87. UMSELn Bits Settings
UMSELn1
UMSELn0
Mode
0
0
1
1
0
Asynchronous USART
Synchronous USART
(Reserved)
1
0
1
Master SPI (MSPIM)
• Bit 5:3 - Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future
devices, these bits must be written to zero when UCSRnC is written.
• Bit 2 - UDORDn: Data Order
When set to one the LSB of the data word is transmitted first. When set to zero the MSB
of the data word is transmitted first. Refer to the Frame Formats section page 4 for
details.
• Bit 1 - UCPHAn: Clock Phase
The UCPHAn bit setting determine if data is sampled on the leasing edge (first) or tailing
(last) edge of XCKn. Refer to the SPI Data Modes and Timing section page 4 for details.
• Bit 0 - UCPOLn: Clock Polarity
The UCPOLn bit sets the polarity of the XCKn clock. The combination of the UCPOLn
and UCPHAn bit settings determine the timing of the data transfer. Refer to the SPI Data
Modes and Timing section page 4 for details.
196
ATmega48/88/168
2545D–AVR–07/04
ATMEL [ ATMEL ]
