ATmega32(L)
Boundary-scan Chain
The Boundary-scan chain has the capability of driving and observing the logic levels on
the digital I/O pins, as well as the boundary between digital and analog logic for analog
circuitry having Off-chip connection.
Scanning the Digital Port Pins Figure 116 shows the Boundary-scan Cell for a bi-directional port pin with pull-up func-
tion. The cell consists of a standard Boundary-scan cell for the Pull-up Enable – PUExn
– function, and a bi-directional pin cell that combines the three signals Output Control –
OCxn, Output Data – ODxn, and Input Data – IDxn, into only a two-stage Shift Register.
The port and pin indexes are not used in the following description.
The Boundary-scan logic is not included in the figures in the datasheet. Figure 117
shows a simple digital Port Pin as described in the section “I/O Ports” on page 49. The
Boundary-scan details from Figure 116 replaces the dashed box in Figure 117.
When no alternate port function is present, the Input Data – ID – corresponds to the
PINxn Register value (but ID has no synchronizer), Output Data corresponds to the
PORT Register, Output Control corresponds to the Data Direction – DD Register, and
the Pull-up Enable – PUExn – corresponds to logic expression PUD · DDxn · PORTxn.
Digital alternate port functions are connected outside the dotted box in Figure 117 to
make the scan chain read the actual pin value. For Analog function, there is a direct
connection from the external pin to the analog circuit, and a scan chain is inserted on
the interface between the digital logic and the analog circuitry.
Figure 116. Boundary-scan Cell for Bidirectional Port Pin with Pull-up Function.
ShiftDR
To Next Cell
EXTEST
Vcc
Pullup Enable (PUE)
0
1
FF2
Q
LD2
0
1
D
D
Q
G
Output Control (OC)
FF1
D Q
LD1
0
1
0
1
D
G
Q
Output Data (OD)
0
1
FF0
D
LD0
0
1
Port Pin (PXn)
0
1
Q
D
G
Q
Input Data (ID)
From Last Cell
ClockDR
UpdateDR
229
2503J–AVR–10/06
ATMEL [ ATMEL ]
